1. F-tile Overview 2. F-tile Architecture 3. Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 4. Implementing the F-Tile Reference and System PLL Clocks Intel® FPGA IP 5. F-tile PMA/FEC Direct PHY Design Implementation 6. Supported Tools 7. Debugging F-Tile Transceiver Links 8. F-tile Architecture and PMA and FEC Direct PHY IP User Guide Archives 9. Document Revision History for F-tile Architecture and PMA and FEC Direct PHY IP User Guide A. Appendix
2.1.1. FHT and FGT PMAs 2.1.2. 400G Hard IP and 200G Hard IP 2.1.3. PMA Data Rates 2.1.4. FEC Architecture 2.1.5. PCIe* Hard IP 2.1.6. Bonding Architecture 2.1.7. Deskew Logic 2.1.8. Embedded Multi-die Interconnect Bridge (EMIB) 2.1.9. IEEE 1588 Precision Time Protocol for Ethernet 2.1.10. Clock Networks 2.1.11. Reconfiguration Interfaces
2.2.1. PMA-to-Fracture Mapping 2.2.2. Determining Which PMA to Map to Which Fracture 2.2.3. Hard IP Placement Rules 2.2.4. IEEE 1588 Precision Time Protocol Placement Rules 2.2.5. Topologies 2.2.6. FEC Placement Rules 2.2.7. Clock Rules and Restrictions 2.2.8. Bonding Placement Rules 2.2.9. Preserving Unused PMA Lanes
220.127.116.11. Implementing One 200GbE-4 Interface with 400G Hard IP and FHT 18.104.22.168. Implementing One 200GbE-2 Interface with 400G Hard IP and FHT 22.214.171.124. Implementing One 100GbE-1 Interface with 400G Hard IP and FHT 126.96.36.199. Implementing One 100GbE-4 Interface with 400G Hard IP and FGT 188.8.131.52. Implementing One 10GbE-1 Interface with 200G Hard IP and FGT 184.108.40.206. Implementing Three 25GbE-1 Interfaces with 400G Hard IP and FHT 220.127.116.11. Implementing One 50GbE-1 and Two 25GbE-1 Interfaces with 400G Hard IP and FHT 18.104.22.168. Implementing One 100GbE-1 and Two 25GbE-1 Interfaces with 400G Hard IP and FHT 22.214.171.124. Implementing Two 100GbE-1 and One 25GbE-1 Interfaces with 400G Hard IP and FHT 126.96.36.199. Implementing 100GbE-1, 100GbE-2, and 50GbE-1 Interfaces with 400G Hard IP and FHT
3.1. F-Tile PMA/FEC Direct PHY Intel® FPGA IP Overview 3.2. Designing with F-Tile PMA/FEC Direct PHY Intel® FPGA IP 3.3. Configuring the IP 3.4. Signal and Port Reference 3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath 3.6. Clocking 3.7. Custom Cadence Generation Ports and Logic 3.8. Asserting Reset 3.9. Bonding Implementation 3.10. Independent Port Configurations 3.11. Configuration Registers 3.12. Configurable Intel® Quartus® Prime Software Settings 3.13. Configuring the F-Tile PMA/FEC Direct PHY Intel® FPGA IP for Hardware Testing 3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.4.1. TX and RX Parallel and Serial Interface Signals 3.4.2. TX and RX Reference Clock and Clock Output Interface Signals 3.4.3. Reset Signals 3.4.4. RS-FEC Signals 3.4.5. Custom Cadence Control and Status Signals 3.4.6. TX PMA Control Signals 3.4.7. RX PMA Status Signals 3.4.8. TX and RX PMA and Core Interface FIFO Signals 3.4.9. PMA Avalon® Memory Mapped Interface Signals 3.4.10. Datapath Avalon® Memory Mapped Interface Signals
3.5.1. Parallel Data Mapping Information 3.5.2. TX and RX Parallel Data Mapping Information for Different Configurations 3.5.3. Example of TX Parallel Data for PMA Width = 8, 10, 16, 20, 32 (X=1) 3.5.4. Example of TX Parallel Data for PMA width = 64 (X=2) 3.5.5. Example of TX Parallel Data for PMA width = 64 (X=2) for FEC Direct Mode
3.8.1. Reset Signal Requirements 3.8.2. Power On Reset Requirements 3.8.3. Reset Signals—Block Level 3.8.4. Reset Signals—Descriptions 3.8.5. Status Signals—Descriptions 3.8.6. Run-time Reset Sequence—TX 3.8.7. Run-time Reset Sequence—RX 3.8.8. Run-time Reset Sequence—TX + RX 3.8.9. Run-time Reset Sequence—TX with FEC
5.1. Implementing the F-tile PMA/FEC Direct PHY Design 5.2. Instantiating the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 5.3. Implementing a RS-FEC Direct Design in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 5.4. Instantiating the F-Tile Reference and System PLL Clocks Intel® FPGA IP 5.5. Enabling Custom Cadence Generation Ports and Logic 5.6. Connecting the F-tile PMA/FEC Direct PHY Design IP 5.7. Simulating the F-Tile PMA/FEC Direct PHY Design 5.8. F-tile Interface Planning
7.2.6. Running Eye Viewer Tests
The Transceiver Toolkit supports internal eye measurements for Intel Agilex® 7 F-Tile devices. The Eye Viewer section in every RX Channel tab under the Channel Parameters pane allows you to set up and run eye measurement tests.
Note: The toolkit does not support 2D Eye plots and it reports the results in terms of Eye Height and Eye Width values.
- Select either Eye Width or Eye Height or both that you want to measure.
- Set Bit Error Rate to measure Eye Width and Bit Error Rate to measure Eye Height as shown in the following figure. Valid bit error rate range is from 1.0E-1 to 1.0E-12. The default bit error rate for NRZ is 1.0E-12, and for PAM4 is 1.0E-4.
Figure 126. Setting the BER and Eye Measurement Options
- Specify the file path to store the results in CSV format.
- Click Start Eye Viewer. Make sure the RX channel is receiving data before starting eye measurement.
When measurement completes, the eye height and eye width results are shown in the following figures. For FGT NRZ signals, the Eye Center-to-top (Middle) and Eye Center-to-bottom (Middle) values are with reference to the center of the eye. Measurement from eye center to the top of the eye is a positive value. Measurement from the eye center to the bottom of the eye is a negative value. The Middle Eye Height is calculated by Eye Center-to-top (Middle) minus Eye Center-to-bottom (Middle). Eye width is reported in units of UI and seconds. For PAM4 signals, eye height of three eyes are shown. The Eye Center-to-top and Eye Center-to-bottom values of the top, middle and bottom eyes are referenced to the center of the middle eye. Measurement above center of the middle eye is a positive value; and measurement below is a negative value. The Eye Height is calculated by Eye Center-to-top minus Eye Center-to-bottom. A negative Eye Height value means the eye is closed. Only the worst eye width of the three eyes is shown.
Figure 127. FGT NRZ Eye Height and Eye Width Results
Figure 128. FGT PAM4 Eye Height and Eye Width Results