E-Tile Hard IP Intel Agilex® 7 Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

ID 683860
Date 8/08/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.2.5. Design Example Register Map for Reconfiguration

Table 21.   E-tile CPRI PHY Intel® FPGA IP Hardware Design Example PHY Register Map
Channel Number Word Offset Register Type
0 0x000000 CPRI registers
0x010000 RS-FEC configuration registers
0x100000 Transceiver registers
1 0x200000 CPRI registers
0x300000 Transceiver registers
2 0x400000 CPRI registers
0x500000 Transceiver registers
3 0x600000 CPRI registers
0x700000 Transceiver registers