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Ixiasoft
Visible to Intel only — GUID: oza1551418090832
Ixiasoft
4.1. Quick Start Guide
The E-Tile Dynamic Reconfiguration Design Example provides a simulation testbench and a hardware design example that supports compilation and hardware testing. When you generate the design example, the parameter editor automatically creates the files necessary to simulate the design in hardware.
In addition, you can download the compiled hardware design to the Intel Agilex® 7 F-Series Transceiver-SoC Development Kit.
Dynamic Reconfiguration Protocol | Variant | Simulation | Hardware Design Example |
---|---|---|---|
10G/25G Ethernet Protocol | 10G/25G with PTP and optional RS-FEC | √ | √ |
10G/25G with optional RS-FEC | √ | √ | |
CPRI | 10G/24G CPRI with optional RS-FEC | √ | √ |
9.8G CPRI | √ | √ | |
25G Ethernet to CPRI Protocol | 25G with PTP and optional RS-FEC | √ | √ |
100G Ethernet Protocol | 100G Ethernet MAC+PCS with optional RS-FEC | √ | √ |
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