184.108.40.206. E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE PCS Only with Optional RS-FEC Simulation Design Example
- Under the IP tab:
- Single 100GE with optional RSFEC or 100GE or 1 to 4 channel 10GE/25GE with optional RSFEC and PTP as the core variant.
- 100GE Channel as Active channel(s) at startup if you choose 100GE or 1 to 4 channel 10GE/25GE with optional RSFEC and PTP as the core variant.
- Under the 100GE tab:
- 100G as the Ethernet rate.
- PCS_Only, PCS+(528,514)RSFEC, or PCS+(544,514)RSFEC as the Ethernet IP layer.
The testbench sends traffic through the IP core, exercising the transmit side and receive side of the IP core.
To speed up simulation, the IP core simulation model sends alignment marker tags at shorter intervals than required by the IEEE Ethernet standard. The standard specifies an alignment marker interval of 16,384 words in each virtual lane. The simulation model with the testbench implements an alignment marker interval of 512 words.
In order to run simulation with the IEEE Ethernet standard specified interval, refer to Non-PTP E-tile Ethernet IP for Intel Agilex 7 FPGA 100GE MAC+PCS with Optional RS-FEC Simulation Design Example for more information.
The successful test run displays output confirming the following behavior:
- The client logic resets the IP core.
- Waits for RX datapath to align.
- Once alignment is complete, client logic transmits a series of packets to the IP core through TX MII interface.
- A counter drives i_tx_mii_am port with alignment marker insertion requests at the correct intervals.
- The client logic receives the same series of packets through RX MII interface.
- The client logic then checks the number of packets received.
- Displaying Testbench complete.
The following sample output illustrates a successful simulation test run for a 100GE, PCS only IP core variation.
o_tx_lanes_stable is 1 at time 354775000 waiting for tx_dll_lock.... TX DLL LOCK is 1 at time 413726943 waiting for tx_transfer_ready.... TX transfer ready is 1 at time 414046815 waiting for rx_transfer_ready.... RX transfer ready is 1 at time 425122383 EHIP PLD Ready out is 1 at time 425184000 EHIP reset out is 0 at time 425320000 EHIP reset ack is 0 at time 426016853 EHIP TX reset out is 0 at time 426232000 EHIP TX reset ack is 0 at time 476830347 waiting for EHIP Ready.... EHIP READY is 1 at time 476910363 EHIP RX reset out is 0 at time 478680000 waiting for rx reset ack.... EHIP RX reset ack is 0 at time 478777403 Waiting for RX Block Lock EHIP Rx Block Lock is high at time 481444603 Waiting for AM lock EHIP Rx am Lock is high at time 482711523 Waiting for RX alignment RX deskew locked RX lane aligmnent locked Sending Packets and Receiving Packets ====> writedata = 00000001 ====>MATCH! ReaddataValid = 1 Readdata = 00000053 Expected_Readdata = 00000053 ** ** Testbench complete. ** *****************************************
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