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2.1.1. Directory Structure
2.1.2. Generating the Design
2.1.3. Simulating the E-tile Ethernet IP for Intel Agilex® 7 FPGA Design Example Testbench
2.1.4. Compiling the Compilation-Only Project
2.1.5. Compiling and Configuring the Design Example in Hardware
2.1.6. Testing the E-tile Ethernet IP for Intel Agilex® 7 FPGA Hardware Design Example
2.2.1.1. Non-PTP 10GE/25GE MAC+PCS with Optional RS-FEC Simulation Design Example
2.2.1.2. PTP 10GE/25GE MAC+PCS with Optional RS-FEC Simulation Design Example
2.2.1.3. 10GE/25GE PCS Only, OTN, or FlexE with Optional RS-FEC Simulation Design Example
2.2.1.4. 10GE/25GE Custom PCS with Optional RS-FEC Simulation Design Example
2.3.1. Simulation Design Examples
2.3.2. Hardware Design Examples
2.3.3. 100GE MAC+PCS with Optional RS-FEC Design Example Interface Signals
2.3.4. 100GE PCS with Optional RS-FEC Design Example Interface Signals
2.3.5. 100GE MAC+PCS with Optional RS-FEC Design Example Registers
2.3.6. 100GE PCS with Optional RS-FEC Design Example Registers
2.3.1.1. Non-PTP E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE MAC+PCS with Optional RS-FEC Simulation Design Example
2.3.1.2. E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE MAC+PCS with Optional RS-FEC and PTP Simulation Design Example
2.3.1.3. E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE PCS Only with Optional RS-FEC Simulation Design Example
2.3.1.4. E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE OTN with Optional RS-FEC Simulation Design Example
2.3.1.5. E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE FlexE with Optional RS-FEC Simulation Design Example
2.3.2.1. 100GE MAC+PCS with Optional RS-FEC and PMA Adaptation Flow Hardware Design Example Components
2.3.2.2. 100GE MAC+PCS with Optional RS-FEC and PTP Hardware Design Example
2.3.2.3. 100GE PCS with Optional RS-FEC Hardware Design Example Components
2.3.2.4. Ethernet Adaptation Flow for 100G (CAUI-2) PAM4 <---> 100G (CAUI-4) NRZ Dynamic Reconfiguration Design Example
3.1.1. Hardware and Software Requirements
3.1.2. Generating the Design
3.1.3. Directory Structure
3.1.4. Simulating the Design Example Testbench
3.1.5. Compiling the Compilation-Only Project
3.1.6. Compiling and Configuring the Design Example in Hardware
3.1.7. Testing the E-tile CPRI PHY Intel® FPGA IP Hardware Design Example
4.1. Quick Start Guide
4.2. 10G/25G Ethernet Dynamic Reconfiguration Design Examples
4.3. 25G Ethernet to CPRI Dynamic Reconfiguration Design Example
4.4. CPRI Dynamic Reconfiguration Design Examples
4.5. 100G Ethernet Dynamic Reconfiguration Design Example
4.6. Document Revision History for the E-tile Dynamic Reconfiguration Design Example
4.5.1. Functional Description
4.5.2. Testing the 100G Ethernet Dynamic Reconfiguration Hardware Design Example
4.5.3. Simulation Design Examples
4.5.4. 100GE DR Hardware Design Examples
4.5.5. 100G Ethernet Dynamic Reconfiguration Design Example Interface Signals
4.5.6. 100G Ethernet Dynamic Reconfiguration Examples Registers
4.5.7. Steps to Enable FEC
4.5.8. Steps to Disable FEC
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2.2.2.3. 10GE/25GE Custom PCS with Optional RS-FEC Hardware Design Example
Figure 12. 10GE/25GE Custom PCS with Optional RS-FEC Hardware Design Example High Level Block Diagram
The E-tile Ethernet IP for Intel Agilex® 7 FPGA hardware design example includes the following components:
- E-tile Ethernet IP for Intel Agilex® 7 FPGA core.
- Client logic that coordinates the programming of the IP core and packet generation.
- JTAG controller that communicates with the System Console. You communicate with the client logic through the System Console.
Result from c3_elane_pcsonly_traffic_basic_test.log file:
Info: Set JTAG Master Service Path Info: Opened JTAG Master Service Test Start time is: 05:47:37 Test Start date is: 03/21/2019 Info: Read all ELANE CSR registers Successfully Read EHIPLANE Channel 0, User Register phy_revid , offset = 0x300, data = 0x11112015 Successfully Read EHIPLANE Channel 0, User Register phy_scratch , offset = 0x301, data = 0x0 . . . Successfully Read EHIPLANE Channel 0, User Register phy_ehip_csr_soft_reset , offset = 0x310, data = 0x0 C3 ELANE Channel 0 System Reset is successfully Info: Stopping the Channel 0 XGMII traffic generator Successfully Read EHIPLANE Channel 0, XGMII Traffic GEN/CHK Register, offset = 0x0, data = 0x0 Successfully Write EHIPLANE Channel 0, XGMII Traffic GEN/CHK Register, offset = 0x0, data = 0x0 Info: Starting the Channel 0 XGMII traffic generator Successfully Write EHIPLANE Channel 0, XGMII Traffic GEN/CHK Register, offset = 0x0, data = 0x1 Info: Comparing the Channel 0 XGMII traffic checker results Successfully Read EHIPLANE Channel 0, XGMII Traffic GEN/CHK Register, offset = 0x2, data = 0x2 Info: Channel 0, Iteration 1 is completed successfully . . . Info: Channel 0, Iteration 5 is completed successfully Info: Channel 0 test is completed Successfully Write EHIPLANE Channel 1, User Register phy_ehip_csr_soft_reset , offset = 0x310, data = 0x0 Successfully Write EHIPLANE Channel 1, User Register phy_ehip_csr_soft_reset , offset = 0x310, data = 0x1 Successfully Write EHIPLANE Channel 1, User Register phy_ehip_csr_soft_reset , offset = 0x310, data = 0x3 Successfully Write EHIPLANE Channel 1, User Register phy_ehip_csr_soft_reset , offset = 0x310, data = 0x7 Successfully Read EHIPLANE Channel 1, User Register phy_ehip_csr_soft_reset , offset = 0x310, data = 0x7 Successfully Write EHIPLANE Channel 1, User Register phy_ehip_csr_soft_reset , offset = 0x310, data = 0x6 Successfully Write EHIPLANE Channel 1, User Register phy_ehip_csr_soft_reset , offset = 0x310, data = 0x4 Successfully Write EHIPLANE Channel 1, User Register phy_ehip_csr_soft_reset , offset = 0x310, data = 0x0 Successfully Read EHIPLANE Channel 1, User Register phy_ehip_csr_soft_reset , offset = 0x310, data = 0x0 C3 ELANE Channel 1 System Reset is successfully Info: Stopping the Channel 1 XGMII traffic generator Successfully Read EHIPLANE Channel 1, XGMII Traffic GEN/CHK Register, offset = 0x0, data = 0x0 Successfully Write EHIPLANE Channel 1, XGMII Traffic GEN/CHK Register, offset = 0x0, data = 0x0 Info: Starting the Channel 1 XGMII traffic generator Successfully Write EHIPLANE Channel 1, XGMII Traffic GEN/CHK Register, offset = 0x0, data = 0x1 Info: Comparing the Channel 1 XGMII traffic checker results Successfully Read EHIPLANE Channel 1, XGMII Traffic GEN/CHK Register, offset = 0x2, data = 0x2 Info: Channel 1, Iteration 1 is completed successfully . . . Info: Channel 1, Iteration 5 is completed successfully Info: Channel 1 test is completed Successfully Read RSFEC Register rsfec_top_rx_cfg , offset = 0x14, data = 0x11 Successfully Read RSFEC Register arbiter_base_cfg , offset = 0x0, data = 0x1 Successfully Read RSFEC Register rsfec_top_clk_cfg , offset = 0x4, data = 0x304 Successfully Read RSFEC Register rsfec_top_tx_cfg , offset = 0x10, data = 0x6611 Successfully Write RSFEC Register rsfec_top_tx_cfg , offset = 0x10, data = 0x10001666 Successfully Read RSFEC Register rsfec_top_tx_cfg , offset = 0x10, data = 0x10001666 Successfully Write RSFEC Register rsfec_top_tx_cfg , offset = 0x10, data = 0x6611 Successfully Read RSFEC Register rsfec_top_tx_cfg , offset = 0x10, data = 0x6611 Test End time is: 05:51:01 Test End date is: 03/21/2019 Info: Closed JTAG Master Service Info: Test <c3_elane_pcsonly_traffic_basic_test> Passed