E-Tile Hard IP Intel Agilex® 7 Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

ID 683860
Date 8/08/2023
Document Table of Contents

3.1.6. Compiling and Configuring the Design Example in Hardware

To compile the hardware design example and configure it on your Intel Agilex® 7 device, follow these steps:

  1. Ensure hardware design example generation is complete.
  2. In the Intel® Quartus® Prime Pro Edition software, open the Intel® Quartus® Prime project <design_example_dir>/hardware_test_design/alt_cpriphy_c3_hw.qpf.
  3. On the Processing menu, click Start Compilation.
  4. After successful compilation, a .sof file is available in <design_example_dir>/hardware_test_design/output_files directory. Follow these steps to program the hardware design example on the Intel Agilex® 7 device:
    1. Connect Intel Agilex® 7 TX Transceiver Signal Integrity Development Kit to the host computer.
      Note: The development kit is preprogrammed with the correct clock frequencies by default. You do not need to use the Clock Control application to set the frequencies.
    2. On the Tools menu, click Programmer.
    3. In the Programmer, click Hardware Setup.
    4. Select a programming device.
    5. Select and add the Agilex 7 TX Transceiver Signal Integrity Development kit to which your Intel® Quartus® Prime Pro Edition session can connect.
    6. Ensure that Mode is set to JTAG.
    7. Select the Intel Agilex® 7 device and click Add Device. The Programmer displays a block diagram of the connections between the devices on your board.
    8. In the row with your .sof, check the box for the .sof.
    9. Check the box in the Program/Configure column.
    10. Click Start.

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