4.5.1. Functional Description
The 100G Ethernet E-Tile Dynamic Reconfiguration Design Example is built from the hardened E-Tile Hard IP for Ethernet IP core to enable run-time reconfiguration between different protocols, rates, and stack layers. The 100G Ethernet E-Tile Dynamic Reconfiguration Design Example supports four PMA channels to create either a single 100G Ethernet channel or four single 10G/25G Ethernet channels. The dynamic reconfiguration interface provides a selection of Ethernet modes to reconfigure your design. Once you select a mode rate, the firmware manages all register space updates to facilitate the rate change.
The dynamic reconfiguration interface enables you to reconfigure the design by selecting specific Ethernet reconfiguration modes. The firmware processes the register space modifications needed to switch between the selected modes. Alternatively, you can reconfigure the individual components by direct register programming.
The IP parameter editor allows you to select the CPU location for the 100G Ethernet E-Tile Dynamic Reconfiguration Design Example. The below figures depict the design examples block diagram with internal and external CPUs.
The usability of the example design with internal and external CPU is the same. The 100G Ethernet Dynamic Reconfiguration design example with external CPU showcase how you can input commands through the CPU through the C-code. The C-code (dynamic_reconfig.cpp) provided in the 100G Ethernet IP files folder serves as a reference for you to modify the input command based on your needs. The C-code is then used to generate a firmware that performs the respective register space modifications.
In the 100G Ethernet Dynamic Reconfiguration design example with internal CPU, you can just rely on the dynamic reconfiguration registers programming to configure the IP into the Ethernet mode required. The internal CPU also executes the firmware to process the necessary register space modifications.
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