Visible to Intel only — GUID: fnu1565650772499
Ixiasoft
Visible to Intel only — GUID: fnu1565650772499
Ixiasoft
4.3.5. 25G Ethernet to CPRI Design Examples Registers
Word Offset |
Register Category |
---|---|
0x000000 – 0x000FFF | Ethernet MAC and PCS registers |
0x001000 – 0x001FFF | Packet Generator and Checker registers |
0x002000 – 0x002FFF | PTP monitoring registers |
0x010000 – 0x0107FF | RS-FEC configuration registers |
0x100000 – 0x1FFFFF | Transceiver registers |
0x003000 – 0x003FFF | CPRI PHY soft registers |
Addr |
Name |
Bit |
Description |
HW Reset Value |
Access |
---|---|---|---|---|---|
0x1000 | PKT_CL_SCRATCH | [31:0] | Scratch register available for testing. | N/A | RW |
0x1001 | PKT_CL_CLNT | [31:0] | Four characters of IP block identification string CLNT. | N/A | RO |
0x1008 | Packet Size Configure | [29:0] | Specify the transmit packet size in bytes. These bits have dependencies to PKT_GEN_TX_CTRL register.
|
0x25800040 | RW |
0x1009 | Packet Number Control | [31:0] | Specify the number of packets to transmit from the packet generator. | 0xA | RW |
0x1010 | PKT_GEN_TX_CTRL | [7:0] |
|
0x6 | RW |
0x1011 | Destination address lower 32 bits | [31:0] | Destination address (lower 32 bits). | 0x56780ADD | RW |
0x1012 | Destination address upper 16 bits | [15:0] | Destination address (upper 16 bits). | 0x1234 | RW |
0x1013 | Source address lower 32 bits | [31:0] | Source address (lower 32 bits). | 0x43210ADD | RW |
0x1014 | Source address upper 16 bits | [15:0] | Source address (upper 16 bits). | 0x8765 | RW |
Addr |
Name |
Bit |
Description |
HW Reset Value |
Access |
---|---|---|---|---|---|
0x3000 | rx_bitslip boundary_ sel | [9:5] | Indicates the number of bits that the 8B/10B RX PCS block slipped to achieve a deterministic latency. | 0x0 | RO |
cpri_fec_en | [4] | Used by deterministic latency, this bit indicates whether the RS-FEC block is enabled.
|
0x1 | RW | |
cpri_rate_ sel | [3:0] | Used by EFIFO and deterministic latency, this bit indicates the CPRI PHY speed selection.
Bit [3:0]:
Note: The TX/RX datapath must be reconfigured after every setting change.
|
0xB | RW | |
0x3001 | dl_reset | [1] | Deterministic Latency (DL) soft reset
Provides a soft reset to the DL block.
Note: This is not a self-clearing reset.
|
0x0 | RW |
measure_ valid | [0] | Indicates whether the deterministic latency measurement values are valid.
|
0x0 | RO | |
0x3002 | tx_delay | [20:0] | TX Datapath Latency Displays the TX datapath deterministic latency measurement values measured in sampling_clk cycles. measure_valid must be set prior taking the measurement. |
0x0 | RO |
0x3003 | rx_delay | [20:0] | RX Datapath Latency Displays the RX datapath deterministic latency measurement values measured in sampling_clk cycles. measure_valid must be set prior taking the measurement. |
0x0 | RO |