F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

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ID 683804
Date 12/19/2022
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example: Single IP Core Instantiation 3. Design Example: Single IP Core Instantiation with Precision Time Protocol 4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training 5. Design Example: Multiple IP Core Instantiation 6. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives 7. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design 1.2. Directory Structure 1.3. Simulating the Design Example Testbench 1.4. Hardware and Software Requirements 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the F-Tile Ethernet Intel FPGA Hard IP Hardware Design Example 1.7. Register Maps
1.1. Generating the Design x
1.1.1. Generating Single IP Instance Design 1.1.2. Generating Multiple IP Instance Design
1.3. Simulating the Design Example Testbench x
1.3.1. Fast Sim Model for FGT Variants 1.3.2. Fast Sim Model for FHT Variants
2. Design Example: Single IP Core Instantiation x
2.1. Features 2.2. Functional Description 2.3. Simulation 2.4. Packet Client Registers
2.2. Functional Description x
2.2.1. Variation: F-Tile Ethernet Intel FPGA Hard IP with FHT PMA
2.3. Simulation x
2.3.1. Simulation Testbench Flow for MAC Mode 2.3.2. Simulation Testbench Flow for PCS, OTN, and FlexE Modes
3. Design Example: Single IP Core Instantiation with Precision Time Protocol x
3.1. Features 3.2. Functional Description 3.3. Simulation 3.4. Hardware Design Example 3.5. Registers
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training x
4.1. Features 4.2. Functional Description 4.3. Simulation 4.4. QSF Assignments 4.5. Hardware Design Example
5. Design Example: Multiple IP Core Instantiation x
5.1. Features 5.2. Functional Description 5.3. Simulation
1. Quick Start Guide
2. Design Example: Single IP Core Instantiation
3. Design Example: Single IP Core Instantiation with Precision Time Protocol
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training
5. Design Example: Multiple IP Core Instantiation
6. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives
7. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide

1.5. Compiling and Configuring the Design Example in Hardware

To compile the hardware design example and configure it on your Intel device, follow these steps:
  1. Ensure hardware design example generation is complete.
  2. In the Intel® Quartus® Prime Pro Edition software, navigate to the Intel® Quartus® Prime project directory eth_f_0_example_design/hardware_test_design/.
  3. Open the Intel® Quartus® Prime project:
    quartus eth_f_hw.qpf &
  4. On the Processing menu, click Start Compilation.
  5. After successful compilation, a .sof file is available in <design_example_directory>/hardware_test_design/output_files.
    • Connect the Agilex I-Series Transceiver-SoC Development Kit to the host computer.
    • Launch the Clock Controller application, which is part of the development kit.
      Figure 8. Clock Controller
      Set new frequencies for the design example as following:
      • Si5394 (U118), OUT3: Set to the value of i_refclk2pll 2 as 156.25MHz.
  6. On the Tools menu, click Programmer.
  7. In the Programmer, click Hardware Setup.
  8. Select a programming device.
  9. Select and add the Development Kit to which your Intel® Quartus® Prime Pro Edition session can connect.
  10. Ensure that Mode is set to JTAG.
  11. Select the device and click Add Device. The Programmer displays a block diagram of the connections between the devices on your board.
  12. In the row with your .sof, check the Program/Configure box for the .sof file.
  13. Click Start.
Note: If the System PLL fails to lock when the i_refclk2pll frequency is greater than 156.25MHz, please refer to the steps specified in Why do F-tile Reference and System PLL clocks Intel® FPGA IP fail to lock at specific frequencies? to resolve the issue.
Related Information
2 The Clock Control GUI application cannot drive all the frequencies.
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