Article ID: 000092708 Content Type: Errata Last Reviewed: 10/26/2022

Why do F-tile Reference and System PLL clocks Intel® FPGA IP fail to lock at specific frequencies?

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in In the Intel® Quartus® Prime Pro Edition Software versions 22.3 and earlier, you may observe the F-tile Reference and System PLL clocks Intel® FPGA IP fails to lock at:

    • 999.9 MHz with the reference clock frequency set as 323.2MHz. 
    • 506.88 MHz with the reference clock frequency set as 245.76MHz.
    Resolution

    To work around this problem, you need to do the following steps:

    1. In the project navigator, double-click the OPN (ordering part number).
    2. In the pop-out window, click the “Device and Pin Options” button.
    3. In the “General” category, change the “Configuration clock source” parameter from “Internal Oscillator” to:                
    • 100 MHz OSC_CLK_1 pin, or
    • 125 MHz OSC_CLK_1 pin
    1. Recompile the design.
    2. Provide an external reference clock with the correct frequency to the OSC_CLK_1 pin. The “OSC_CLK_1” pin location can be found in the schematics of your development kit.

    Note: for Intel® Agilex™ F-tile devices with OPNs that end with the suffix VR0, VR1, and VR2, you need to use Intel® Quartus® Prime Programmer version 21.4 to get the above workarounds working.

     

    Related Products

    This article applies to 1 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs

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