F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

ID 683804
Date 12/19/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

1.3.2. Fast Sim Model for FHT Variants

To provide a reduction in a real-time simulation duration, you can utilize a Fast Sim model in your design example testbench. For FHT variants, the model is enabled by a macro in the simulation run script.
To enable the Fast Sim model, add the following macro to your simulation run script:
+define+gdrb_BK_FASTSIM_MODEL
Note: The design example simulation script does not enable the macro by default. You need to manually add the macro.