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3.2. Functional Description
When generating a design example with PTP option enabled, the software instantiates PTP-specific components.
Figure 12. F-Tile Ethernet Intel FPGA Hard IP: Design Example with Enabled PTP
The F-Tile Ethernet Intel FPGA Hard IP design example includes the following components:
- F-Tile Ethernet Intel FPGA Hard IP : Generated IP core with enabled PTP option.
- F-Tile Reference and System PLL Clocks Intel® FPGA IP : Instantiate reference clock and system PLL. For information about supported system PLL modes, refer to F-Tile Ethernet Intel FPGA Hard IP . For information about this IP, refer to F-Tile Architecture and PMA and FEC Direct PHY IP User Guide.
- Time-of-Day (TOD): Provides a continuous flow of a current time-of-day information to the IP core. The master TOD runs at 100 MHz clock frequency. TX TOD and RX TOD, which are clocked by div66 or div68 clock of the F-Tile Ethernet Intel FPGA Hard IP, synchronize to the master TOD through their respective TOD synchronizers.
Master TOD also generates a one pulse per second (1 pps) to monitor the accuracy and allows synchronization between multiple devices.
In this user guide, the generated design example assumes 0 ppm delay. In your design, drive the master TOD with the most accurate clock.
- Packet Client: Consists of multiple PTP related modules. The Packet Client does not support the PTP functionality when packet loop back is set from RX to TX in client side.
- Packet Generator: Configures to loop over various patterns in the ROM. Alternatively, can perform a single transmission.
- PTP Command Generator: The PTP command generation module in the Packet Client generates PTP command for the packet in transmission. The generated command aligns to start-of-packet (SOP) for Avalon® streaming interface and MAC segmented based interface.
- Packet Monitor: Stores sent and received packet information between packet client and the IP core.
- PTP Monitor: The module stores the PTP information sent from/to the Packet Client to/from the F-Tile Ethernet Intel FPGA Hard IP when packet loop backs from TX serial to RX serial.
Note: PTP Monitor can store and read 16 packets of 128 bytes in length. Sending more packets without first reading the contents of the PTP monitor can cause unexpected results.
- PTP Adapter Module ( Avalon® memory-mapped interface for Asymmetry and Peer-to-Peer (P2P): If you enabled PTP option in the F-Tile Ethernet Intel FPGA Hard IP, you must instantiate this module and connect it to all associated Ethernet IP cores. The design allows only one instance per tile.
When instantiated, the module provides the access to the Avalon® memory-mapped interface registers, specifically Asymmetry Delay and P2P MeanPathDelay registers.
- Avalon® memory-mapped interface Decoder: Decodes the Avalon® memory-mapped interface address to Hardware IP Top, master TOD, and PTP adapter. For base address for each of the Avalon® memory-mapped interface accessed instances, refer to Register Maps.
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