F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

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ID 683804
Date 12/19/2022
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example: Single IP Core Instantiation 3. Design Example: Single IP Core Instantiation with Precision Time Protocol 4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training 5. Design Example: Multiple IP Core Instantiation 6. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives 7. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design 1.2. Directory Structure 1.3. Simulating the Design Example Testbench 1.4. Hardware and Software Requirements 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the F-Tile Ethernet Intel FPGA Hard IP Hardware Design Example 1.7. Register Maps
1.1. Generating the Design x
1.1.1. Generating Single IP Instance Design 1.1.2. Generating Multiple IP Instance Design
1.3. Simulating the Design Example Testbench x
1.3.1. Fast Sim Model for FGT Variants 1.3.2. Fast Sim Model for FHT Variants
2. Design Example: Single IP Core Instantiation x
2.1. Features 2.2. Functional Description 2.3. Simulation 2.4. Packet Client Registers
2.2. Functional Description x
2.2.1. Variation: F-Tile Ethernet Intel FPGA Hard IP with FHT PMA
2.3. Simulation x
2.3.1. Simulation Testbench Flow for MAC Mode 2.3.2. Simulation Testbench Flow for PCS, OTN, and FlexE Modes
3. Design Example: Single IP Core Instantiation with Precision Time Protocol x
3.1. Features 3.2. Functional Description 3.3. Simulation 3.4. Hardware Design Example 3.5. Registers
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training x
4.1. Features 4.2. Functional Description 4.3. Simulation 4.4. QSF Assignments 4.5. Hardware Design Example
5. Design Example: Multiple IP Core Instantiation x
5.1. Features 5.2. Functional Description 5.3. Simulation
1. Quick Start Guide
2. Design Example: Single IP Core Instantiation
3. Design Example: Single IP Core Instantiation with Precision Time Protocol
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training
5. Design Example: Multiple IP Core Instantiation
6. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives
7. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide

4.3. Simulation

The testbench provides basic functionality such as the startup and waits for lock and send and receive a few packets using the ROM-based packet generator.
Important: Before the simulation, you must generate tile-related files and specify the colocate assignment in the .qsf file to map F-Tile Auto-Negotiation and Link Training for Ethernet Intel® FPGA IP to the F-Tile Ethernet Intel FPGA Hard IP for successful simulation as shown below.
  1. Append the eth_f_hw.qsf file as shown below:
    • Use the following syntax to colocate assignments:
      set_instance_assignment -name IP_COLOCATE \
-from <ANLT IP hierarchical path>  -to <Ethernet hierarchical path> <tile type>
    • Example:
      set_instance_assignment -name IP_COLOCATE \
-from kr_dut|eth_anlt_f_0 -to IP_INST[0].hw_ip_top|dut|eth_f_0 F_TILE
  2. At the command prompt, navigate to the hardware_test_design folder in your example design:
    cd <your_design_path>/hardware_test_design
  3. Run the following command to generate eth_f_hw_tiles files:
    quartus_tlg eth_f_hw
  4. At the command prompt, change to the testbench simulation directory.
    CD <design_example_dir>/ex_*G/sim
  5. Run the IP setup simulation:
    ip-setup-simulation --quartus project=../../hardware_test_design/eth_f_hw.qpf
  6. Add the following macro to your simulation run script for AN/LT enabled designs:
    • For FGT
      +define+INTC_SIM_AN_LT_ENABLE
    • For FHT
      +define+RTL
    Note: In generated design example, the colocate assignments are already available in qsf file by default. Therefore, steps 1 to 5 can be skipped in the design example.
Figure 14.  F-Tile Ethernet Intel FPGA Hard IP Simulation Design Example Block Diagram with Enabled Auto-Negotiation and Link Training
The following steps show the simulation testbench flow:
  1. Assert global resets (i_rst_n and i_reconfig_rst) to reset the F-Tile Ethernet Intel FPGA Hard IP and F-Tile Auto-Negotiation and Link Training for Ethernet Intel® FPGA IP.
  2. Wait until configuration settings load.
  3. Wait until resets acknowledgment. The o_rst_ack_n signal goes low.
  4. Deasserts the global resets, i_rst_n and i_reconfig_rst.
  5. Wait until auto-negotiation is complete. The data mode begins.
  6. Wait until link training is complete.
  7. Wait until o_tx_lanes_stable bit is set to 1, indicating TX path is ready.
  8. Wait until o_rx_pcs_ready bit is set to 1, indicating RX path is ready.
  9. Instruct packet client to transmit data. Write hw_pc_ctrl[0]=1'b1 to start the packet generator.
  10. Read TX packet data information from 0x20 - 0x34 registers. Read register in sequential order.
  11. Read RX packet data information from 0x38 - 0x4C registers. Read register in sequential order.
  12. Compare the counters to ensure 16 packets were sent and received.
  13. Instruct packet client to stop data transmission. Write hw_pc_ctrl[2:0]=3'b100 to stop the packet generator. Clear counters.
  14. Perform Avalon® memory-mapped interface test. Write and read Ethernet IP registers.
    • 0x104: Scratch register
    • 0x108: IP soft reset register
    • 0x214: TX MAX source address register [31:0]
    • 0x218: TX MAX source address register [47:32]
    • 0x21C: RX MAX frame size register
  15. Perform Avalon® memory-mapped interface 2 test to read and write operation transceiver registers.
The following sample output illustrates a successful simulation test run. 
---TX reset sequence completed -----
---RX reset sequence completed -----
---Starting Data mode after completing AN ----
---IP_INST[ 0] Test    0;   ---Total     16 packets to send-----
------IP_INST[ 0] Start pkt gen TX-----
------Checking Packet TX/RX result-----
------------  16 packets Sent;     0 packets Received--------
------ALL   16  packets Sent out---
------------  16 packets Sent;    16 packets Received--------
------ALL   16  packets Received---
------TX/RX packet check OK---
****Starting AVMM Read/Write****
====>MATCH!     ReaddataValid = 1 Readdata = abcdef01 Expected_Readdata = abcdef01 
====>MATCH!     ReaddataValid = 1 Readdata = 00000007 Expected_Readdata = 00000007 
====>MATCH!     ReaddataValid = 1 Readdata = 00000000 Expected_Readdata = 00000000 
====>MATCH!     ReaddataValid = 1 Readdata = 9d228c3a Expected_Readdata = 9d228c3a 
====>MATCH!     ReaddataValid = 1 Readdata = 4338b586 Expected_Readdata = 4338b586 
====>MATCH!     ReaddataValid = 1 Readdata = deadc0de Expected_Readdata = deadc0de 
====>MATCH!     ReaddataValid = 1 Readdata = deadc0de Expected_Readdata = deadc0de 
====>MATCH!     ReaddataValid = 1 Readdata = 00000000 Expected_Readdata = 00000000 
====>MATCH!     ReaddataValid = 1 Readdata = 22334455 Expected_Readdata = 22334455 
====>MATCH!     ReaddataValid = 1 Readdata = 00000011 Expected_Readdata = 00000011 
====>MATCH!     ReaddataValid = 1 Readdata = 000005ee Expected_Readdata = 000005ee 
====>MATCH!     ReaddataValid = 1 Readdata = 01234567 Expected_Readdata = 01234567 
====>MATCH!     ReaddataValid = 1 Readdata = 000089ab Expected_Readdata = 000089ab 
743830ns  Try to access AVMM2 begin...
743830ns  write 0x00000065 to xcvr  0 address 0x103c004
744795ns  Try to access AVMM2 end...
744890ns  read from address 0x103c004
====>MATCH!     ReaddataValid = 1 Readdata = 00000065 Expected_Readdata = 00000065 

...

758740ns  Try to access AVMM2 end...
758840ns  Try to access AVMM2 begin...
758840ns  write 0x0000006c to xcvr  7 address 0x103c00b
759825ns  Try to access AVMM2 end...
759920ns  read from address 0x103c00b
====>MATCH!     ReaddataValid = 1 Readdata = 0000006c Expected_Readdata = 0000006c 
760900ns  Try to access AVMM2 end...
**** AVMM Read/Write Operation Completed for IP_INST[ 0]****
** Testbench complete
**
Note: The simulation completion may take a longer time. To confirm the simulation is progressing successfully, verify the intermediate outputs from the System Console such as bringing the base and AN/LT IP out of resets, IP resetting sequence, Auto-negotiation and link training auto-connection completion, and others.
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