F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

Download PDF
ID 683804
Date 12/19/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example: Single IP Core Instantiation 3. Design Example: Single IP Core Instantiation with Precision Time Protocol 4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training 5. Design Example: Multiple IP Core Instantiation 6. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives 7. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design 1.2. Directory Structure 1.3. Simulating the Design Example Testbench 1.4. Hardware and Software Requirements 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the F-Tile Ethernet Intel FPGA Hard IP Hardware Design Example 1.7. Register Maps
1.1. Generating the Design x
1.1.1. Generating Single IP Instance Design 1.1.2. Generating Multiple IP Instance Design
1.3. Simulating the Design Example Testbench x
1.3.1. Fast Sim Model for FGT Variants 1.3.2. Fast Sim Model for FHT Variants
2. Design Example: Single IP Core Instantiation x
2.1. Features 2.2. Functional Description 2.3. Simulation 2.4. Packet Client Registers
2.2. Functional Description x
2.2.1. Variation: F-Tile Ethernet Intel FPGA Hard IP with FHT PMA
2.3. Simulation x
2.3.1. Simulation Testbench Flow for MAC Mode 2.3.2. Simulation Testbench Flow for PCS, OTN, and FlexE Modes
3. Design Example: Single IP Core Instantiation with Precision Time Protocol x
3.1. Features 3.2. Functional Description 3.3. Simulation 3.4. Hardware Design Example 3.5. Registers
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training x
4.1. Features 4.2. Functional Description 4.3. Simulation 4.4. QSF Assignments 4.5. Hardware Design Example
5. Design Example: Multiple IP Core Instantiation x
5.1. Features 5.2. Functional Description 5.3. Simulation
1. Quick Start Guide
2. Design Example: Single IP Core Instantiation
3. Design Example: Single IP Core Instantiation with Precision Time Protocol
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training
5. Design Example: Multiple IP Core Instantiation
6. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives
7. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide

4.5. Hardware Design Example

Follow these steps to test Ethernet-based design examples with enabled auto-negotiation and link training in hardware:
  1. Generate design example as described in Generating the Design.
  2. Modify the .qsf settings:
    • Set device to match the appropriate ordering part number (OPN) for your design.
    • Update the pinout to match the board and the design function.
    • Assign the appropriate VID settings in your .qsf file to match your board.
  3. Generate the .sof file.
  4. Update board clock settings. The default value for the PHY reference clock is 156.25 MHz. The default value for the reconfiguration clock is 100 MHz.
  5. Insert appropriate electrical loopback plug into the Ethernet port.
  6. Program the design.
  7. Open Tools > System Debugging Tools > System Console.
  8. Navigate to the hardware directory <design_example>/hardware_test_design/hwtest directory.
  9. Type source main_<variant_type>.tcl.
  10. Type set_jtag<number_of appropriate_JTAG_master>
  11. Perform this step if external loopback module is connected. Skip this step if the design connects to link partner.
    1. Type command to read the seq cfg register:
      reg_read 0x101002C0
    2. Type command to set the ignore nonce value to 1:
      Note:
      • For Ethernet modes (50GE-1, 100GE-2, and 200GE-4) with FEC mode (Ethernet Technology Consortium RS(272, 258)), write to 
        reg_write 0x10100300 0x737d0381
      • For Ethernet modes (25GE-1, 50GE-2, and 400GE-8) with any FEC mode, write to 
        reg_write 0x10100300 0x737d0381
      • For other Ethernet modes: 
        reg_write 0x10100300 0x737d0281
    3. Type command to restart the AN sequencer:
      reg_write 0x101002c0 0x00002003
    4. Type command to read the debug status:
      reg_read 0x101003c0
      The link is up if the command returns value 1f0.
  12. Type the command to check the PHY status:
    chkphy_status
  13. Type the command to start and stop the packet generator. The function sends 16 packets.
    start_pkt_gen
stop_pkt_gen
  14. Type the command to check the MAC status:
    chkmac_status

The following sample output illustrates a successful hardware test:


% set_jtag 10
Currently selected master is 10:
/devices/AGIB027R29AR(0|1|2|3)@1#USB-1#AGI FPGA Development kit#sj-appslaba-400.altera.priv.altra.com/(link)/JTAG/(110:132 V1 #0)/phy_0/master/channels/local/mylib/master_1
% reg_read 0x101002c0
0xdeadc0de
% reg_read 0x101002c0
0x00002002
% reg_read 0x10100300
0x737d0201
% reg_write 0x10100300 0x737d0281
0
% reg_read 0x10100300
0x737d0281
% reg_write 0x101002c0 0x2003
0
% reg_read 0x101002c0
0x00002002
% reg_read 0x101003c0
0x000001f0
% chkphy_status
RX PHY Register Access: Checking Clock Frequencies (KHZ)
       TXCLK   :40283 (KHZ)
       RXCLK   :40285 (KHZ)
TX PLL Lock Status        0x0000000f
Rx Frequency Lock Status  0x0000000f
RX PCS Ready              0x1
TX lanes Stable           0x1
Deskewed Status           0x1
Link Fault Status         0x00000000
Rx Frame Error            0x00000000
Rx Am LOCK Condition      0x1

% start_pkt_gen
0
% stop_pkt_gen
0
% Chkmac_stats
====================================================================
                      STATISTICS FOR BASE 12288 (Rx)
====================================================================
Fragmented Frames              :0
Jabbered Frames                :0
Any Size with FCS Err Frame    :0
Right Size with FCS Err Fra    :0
Multicast data Err Frames      :0
Broadcast data Err Frames      :0
Unicast data Err Frames        :0
Multicast Control Err Frames   :0
Broadcast Control Err Frames   :0
Unicast Control Err Frames     :0
pause Control Err Frames       :0
64 Byte Frames                 :0
65 - 127 Byte Frames           :32
128 - 255 Byte Frames          :1
256 - 511 Byte Frames          :0
512 - 1023 Byte Frames         :1
1024 - 1518 Byte Frames        :0
1519 - MAX Byte Frames         :0
> MAX Byte Frames              :0
Rx Frame Startes               :34
Multicast data OK Frame        :33
Broadcast data OK Frame        :0
Unicast Data OK Frame          :0
Multicast Control Frames       :0
Broadcast Control Frames       :0
Unicast Control Frames         :0
Pause Control Frames           :0
Data and Padding Octets        :2671
Frame Octets                   :3283
--------------------------------------------------------------------
====================================================================      
                      STATISTICS FOR BASE 12288 (Tx)
====================================================================
Fragmented Frames              :0
Jabbered Frames                :0
Any Size with FCS Err Frame    :0
Right Size with FCS Err Fra    :0
Multicast data Err Frames      :0
Broadcast data Err Frames      :0
Unicast data Err Frames        :0
Multicast Control Err Frames   :0
Broadcast Control Err Frames   :0
Unicast Control Err Frames     :0
pause Control Err Frames       :0
64 Byte Frames                 :0
65 - 127 Byte Frames           :32
128 - 255 Byte Frames          :1
256 - 511 Byte Frames          :0
512 - 1023 Byte Frames         :1
1024 - 1518 Byte Frames        :0
1519 - MAX Byte Frames         :0
> MAX Byte Frames              :0
Tx Frame Startes               :34
Multicast data OK Frame        :33
Broadcast data OK Frame        :0
Unicast Data OK Frame          :0
Multicast Control Frames       :0
Broadcast Control Frames       :0
Unicast Control Frames         :0
Pause Control Frames           :0
Data and Padding Octets        :2671
Frame Octets                   :3283
0
%
-------------------------------------------------------------------
Level Two Title