1. Quick Start Guide 2. Design Example: Single IP Core Instantiation 3. Design Example: Single IP Core Instantiation with Precision Time Protocol 4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training 5. Design Example: Multiple IP Core Instantiation 6. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives 7. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide
- Supports 10G, 25G, 50G, 100G, 200G, and 400G Ethernet rates
- Supports Avalon® streaming interface for 10G, 25G, 50G, and 100G Ethernet rates with synchronous or asynchronous adapter
- Supports MAC segmented interface for all Ethernet rates
- Instantiates PTP adapter module (eth_ptp_adpt_f)
- Instantiates Ethernet IEEE 1588 TOD and TOD Synchronizer Intel® FPGA IP based on Ethernet configuration
- Instantiates F-Tile Reference and System PLL Clocks Intel® FPGA IP based on Ethernet configuration
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