ID 683804
Date 12/19/2022
Public

## 3.4. Hardware Design Example

Follow these steps to test Ethernet-based design examples with enabled PTP in hardware:
1. Generate design example as described in Generating the Design.
2. Set up the design example hardware test using Agilex I-Series Transceiver-SoC Development Kit as described in Compiling and Configuring the Design Example in Hardware.
3. Launch the Clock Control application, which is part of the development kit, and set new frequencies for the design example as described below. Below is the frequency setting in the Clock Control application.
• Si5394, OUT3—156.25 MHz (i_refclk2pll)
• Si5332, OUT1—125 MHz (i_clk_master_tod)
Note: The PHY reference clock default value is 156.25 MHz. The reconfiguration clock default value is 100 MHz.
4. Insert the appropriate electric look back plug into the Ethernet port.
5. If you enabled Advanced Timestamp Accuracy Mode, generate routing delay.
• After successful compilation, navigate to the <design_example>/hardware_test_design directory.
• Copy <design_example>/ex_<speed>/eth_f_<version>/synth/eth_f_ptp_report_dl_path_delay.tcl to the current directory.
• Run the script:
quartus_sta -t eth_f_ptp_report_dl_path_delay.tcl eth_f_hw
6. Update the script with the loopback module's delay. This is an optional step if timestamp accuracy is not a concern.
1. Open the <design_example>/hardware_test_design/hwtest/altera/ptp/ptp_params.tcl file.
2. Locate set PHY_DLY command based on the <xcvr_type> transceiver type and the <apl> physical lane number. For example, the following line specifies the channel placed at top-most FGT lane:
set PHY_DLY(lpbk_module_dly,0,15)
3. Modify the <delay_value> delay value of loopback module channel. The default value is set to 0.
Repeat steps b and c for all active channels.
Note: The tx_board_dly and rx__board_dly values provided in the ptp_params.tcl file are specific to the selected development kit. You must update these values, if you are running the script on a different board.
7. Navigate to the <design_example>/hardware_test_design/hwtest directory.
8. Open Tools > System Debugging Tools > System Console.
9. Run the following command in the Tcl shell:
source main_<Ethernet_rate>_ptp.tcl
set_jtag<number_of appropriate_JTAG_master>

10. Run the following command:
run_test
The test sends and receives 16 packets. The entire output file is available in the <design_example>/hardware_test_design/hwtest/ptp_log.txt file.
The following sample output illustrates a successful hardware test:
--09:59:46-- Info: PTP Initialization beginning...

Ethernet Variant: 3
ui:               0x004D19EC
VL:               16
PL_FL_MAP:        2
tx_pma_delay_ui:  158
rx_pma_delay_ui:  175

#=================================================
--09:59:46-- Info: Initializing TX PTP for IP_INST[0]
=================================================#
--09:59:46-- Info: Wait for TX PTP offset data valid assertion
--09:59:46-- Info: TX PTP offset data valid asserted
--09:59:46-- Info: Reading TX raw offset data
--09:59:46-- Info: Determine TX reference lane
tx_ref_pl:               0x6
tx_am_actual_time_max:   0xd153f98
--09:59:46-- Info: Calculate TX offsets
tx_const_delay:        0x9EE
tx_const_delay_sign:   0x0
tx_ref_pl:             6

(more content …)
-09:59:46-- Info:     TX PTP ready asserted.
#=================================================
--09:59:46-- Info: Initializing RX PTP for IP_INST[0]
=================================================#
--09:59:46-- Info: Wait for RX PCS fully aligned assertion
--09:59:46-- Info:    50G to 400G FEC variant - RX PCS & RX FEC locked
--09:59:46-- Info: FEC variant... proceed to rx_fec_codeword_position step

(more content …)
--09:59:46-- Info: RX PTP ready asserted.
--09:59:46-- Info: PTP Initialization completed!
--09:59:46-- Info: Programming ASYM/P2P Register for demonstration
0x00000100 was written to 0x10015044
Verifying write data by re-reading 0x10015044
0x00000200 was written to 0x10015048
Verifying write data by re-reading 0x10015048
0x00000200 was written to 0x10025048
Verifying write data by re-reading 0x10025048
--09:59:46-- Info: Programming ASYM/P2P Register completed!

--09:59:47-- Info: Checking PTP packets
--09:59:47-- Info: Wait for TX Packet Valid to assert
--09:59:47-- Info: TX Packet Valid detected

Frame monitored by frame_parser TX
Frame Length : 128
Empty : 0
----------------------------------------------------------
|  00 01 02 03 04 05 06 07  08 09 10 11 12 13 14 15
----------------------------------------------------------
0000 |  AB E4 23 39 F0 00 1E 84  33 9F 01 00 88 F7 00 00
0010 |  30 31 32 33 AA 35 36 AA  38 39 3A 3B 3C 3D 3E 3F
0020 |  40 41 42 43 BB CC 46 47  48 49 4A 4B 4C 4D 4E 4F
0030 |  50 51 52 53 54 55 56 57  BB CC 5A 5B 5C 5D 5E 5F
0040 |  60 61 62 63 64 65 66 67  68 69 6A 6B 6C 6D 6E 6F
0050 |  70 71 72 73 74 75 76 77  78 79 7A 7B 7C 7D 7E 7F
0060 |  80 81 82 83 84 85 86 87  88 89 8A 8B 8C 8D 8E 8F
0070 |  90 91 92 93 94 95 96 97  98 99 9A 9B 9C 9D 9E 9F
----------------------------------------------------------

--09:59:48-- Info: Reading TX PTP Commands
--09:59:48-- Info: Reading TX Egress Timestamp
--09:59:48-- Info: Wait for RX Packet Valid to assert
--09:59:48-- Info: RX Packet Valid detected
--09:59:48-- Info: Reading RX Ingress Timestamp
Frame monitored by frame_parser RX
Frame Length : 128
Empty : 0
----------------------------------------------------------
|  00 01 02 03 04 05 06 07  08 09 10 11 12 13 14 15
----------------------------------------------------------
0000 |  AB E4 23 39 F0 00 1E 84  33 9F 01 00 88 F7 00 00
0010 |  30 31 32 33 AA 35 36 AA  38 39 3A 3B 3C 3D 3E 3F
0020 |  40 41 42 43 BB CC 46 47  48 49 4A 4B 4C 4D 4E 4F
0030 |  50 51 52 53 54 55 56 57  BB CC 5A 5B 5C 5D 5E 5F
0040 |  60 61 62 63 64 65 66 67  68 69 6A 6B 6C 6D 6E 6F
0050 |  70 71 72 73 74 75 76 77  78 79 7A 7B 7C 7D 7E 7F
0060 |  80 81 82 83 84 85 86 87  88 89 8A 8B 8C 8D 8E 8F
0070 |  90 91 92 93 94 95 96 97  98 99 9A 9B 9C 9D 9E 9F
----------------------------------------------------------

------------------------------
TX PTP Command #1
------------------------------
Egress Timestamp Request            : 1
Insert Timestamp                    : 0
Update CorrectionField              : 0
Clear UDP/IPv4 Checksum             : 0
Update UDP/IPv6 Extended Bytes      : 0
Add Peer-to-Peer (P2P) MinPathDelay : 0
Asymmetry Delay Sign                : 0
Asymmetry & P2P MinPathDelay Select : 0x0
Timestamp Field Offset              : 0x0000
Correction Field Offset             : 0x0000
TX Fingerprint Data                 : 0x00000001
TX Ingress Timestamp                : 0x000000000024000000000000
------------------------------
Timestamps #1
------------------------------
TX Egress Timestamp                 : 0x0000000000241cb8ed9c6280
RX Ingress Timestamp                : 0x0000000000241cb8ed9d6c80
TX User Fingerprint                 : 0x00000001
TX Returned Fingerprint             : 0x00000001
------------------------------
Comparison #1
------------------------------
RX_ITS - TX_ETS       : 0x10a00/1.0391 ns
TX Timestamp Fields   : 0x5051525354555657BBCC
RX Timestamp Fields   : 0x5051525354555657BBCC
TX Correction Fields  : 0x36AA38393A3B3C3D
RX Correction Fields  : 0x36AA38393A3B3C3D


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