F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

Download PDF
ID 683804
Date 12/19/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example: Single IP Core Instantiation 3. Design Example: Single IP Core Instantiation with Precision Time Protocol 4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training 5. Design Example: Multiple IP Core Instantiation 6. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives 7. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design 1.2. Directory Structure 1.3. Simulating the Design Example Testbench 1.4. Hardware and Software Requirements 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the F-Tile Ethernet Intel FPGA Hard IP Hardware Design Example 1.7. Register Maps
1.1. Generating the Design x
1.1.1. Generating Single IP Instance Design 1.1.2. Generating Multiple IP Instance Design
1.3. Simulating the Design Example Testbench x
1.3.1. Fast Sim Model for FGT Variants 1.3.2. Fast Sim Model for FHT Variants
2. Design Example: Single IP Core Instantiation x
2.1. Features 2.2. Functional Description 2.3. Simulation 2.4. Packet Client Registers
2.2. Functional Description x
2.2.1. Variation: F-Tile Ethernet Intel FPGA Hard IP with FHT PMA
2.3. Simulation x
2.3.1. Simulation Testbench Flow for MAC Mode 2.3.2. Simulation Testbench Flow for PCS, OTN, and FlexE Modes
3. Design Example: Single IP Core Instantiation with Precision Time Protocol x
3.1. Features 3.2. Functional Description 3.3. Simulation 3.4. Hardware Design Example 3.5. Registers
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training x
4.1. Features 4.2. Functional Description 4.3. Simulation 4.4. QSF Assignments 4.5. Hardware Design Example
5. Design Example: Multiple IP Core Instantiation x
5.1. Features 5.2. Functional Description 5.3. Simulation
1. Quick Start Guide
2. Design Example: Single IP Core Instantiation
3. Design Example: Single IP Core Instantiation with Precision Time Protocol
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training
5. Design Example: Multiple IP Core Instantiation
6. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives
7. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide

5.2. Functional Description

Figure 15. Simulation Design Example Block for Multiple F-Tile Ethernet Intel FPGA Hard IPs
The F-Tile Ethernet Intel FPGA Hard IP design example includes the following components:
  • F-Tile Ethernet Intel FPGA Hard IP : Generated IP core.
  • F-Tile Reference and System PLL Clocks Intel® FPGA IP : Instantiated reference clock and system PLL clock IP. The F-Tile Reference and System PLL Clocks Intel® FPGA IP parameter editor settings align with the System PLL frequency and PMA reference frequency parameter settings in the F-Tile Ethernet Intel FPGA Hard IP. If you generate the design example using Generate Example Design button in the IP parameter editor, the IP instantiates automatically. If you create your own design example, you must manually instantiate this IP and connect all I/O ports.

    For information about supported system PLL modes, refer to F-Tile Ethernet Intel FPGA Hard IP User Guide. For information about this IP, refer to F-Tile Architecture and PMA and FEC Direct PHY IP User Guide.

  • Packet Client: Consists of a packet generator, a packet checker and a loopback client. The Packet Client generates various ROM-based traffic patterns for MAC mode and can loopback the RX and TX client side.
  • Avalon® memory-mapped interface Decoder: Decodes the Avalon® memory-mapped interface address to Hardware IP Top and PTP blocks if PTP is enabled. For base address for each of the Avalon® memory-mapped interface accessed instances, refer to Register Maps.
Related Information
Level Two Title