Agilex™ 7 Clocking and PLL User Guide: F-Series and I-Series

ID 683761
Date 4/01/2024
Document Table of Contents

1.2. PLLs Overview

Phase-locked loops (PLLs) provide robust clock management and synthesis for device clock management, external system clock management, and high-speed I/O interfaces.

The Agilex™ 7 FPGA F-Series and I-Series devices contain the following I/O PLLs for core applications. The I/O PLLs can only function as integer PLLs.

  • Fabric-feeding I/O PLLs—three C counter outputs available and support PLL cascading. However, Fabric-feeding I/O PLL to Fabric-feeding I/O PLL cascading is not supported.
  • I/O bank I/O PLLs—seven C counter outputs available and support PLL cascading

The I/O PLLs are located adjacent to the hard memory controllers and LVDS serializer/deserializer (SERDES) blocks in the I/O banks. Each I/O bank contains two I/O bank I/O PLLs and one fabric-feeding I/O PLL.