Agilex™ 7 Clocking and PLL User Guide: F-Series and I-Series

ID 683761
Date 4/01/2024
Document Table of Contents

5. IOPLL Intel® FPGA IP Core

The IOPLL IP core allows you to configure the settings of the F-Series and I-Series I/O PLL.

The IOPLL IP core supports the following features:

  • Supports six different clock feedback modes: direct, external feedback, normal, source synchronous, zero delay buffer, and LVDS mode.
  • Generates up to seven output clocks for I/O bank I/O PLL and three output clocks for fabric-feeding I/O PLL for the F-Series and I-Series device.
  • Switches between two reference input clocks.
  • Supports adjacent PLL (adjpllin) input to connect with an upstream PLL in PLL dedicated cascading mode.
  • Generates the Memory Initialization File (.mif) and allows PLL dynamic reconfiguration.
  • Supports PLL dynamic phase shift.