Agilex™ 7 Clocking and PLL User Guide: F-Series and I-Series

ID 683761
Date 4/01/2024
Document Table of Contents

6.6.3. Reconfiguration Option: Clock Gating Reconfiguration Using IOPLL Reconfig IP Core

After the I/O PLL reconfiguration operation is complete, the I/O PLL operates in the following configuration at medium bandwidth:

  • Counter C1 output is ungated
  • Counter C2 output is gated

To run the design example using clock gating reconfiguration, perform these steps:

  1. Open AN.stp file and program the device top.sof.
  2. In the In-System Sources & Probes IP core, keep mode_0 in low pulse and assert mode_1 to high pulse.
  3. Assert a high pulse on the reset_SM signal to start the I/O PLL reconfiguration operation.
Figure 27. Waveform Example for Clock Gating Reconfiguration Design Example