Agilex™ 7 Clocking and PLL User Guide: F-Series and I-Series

ID 683761
Date 4/01/2024
Document Table of Contents

4.2. Clock Control Intel® FPGA IP Core Parameters

Table 5.   Clock Control Intel® FPGA IP Core Parameters for F-Series and I-Series Devices
Parameter Value Description
Number of Clock Inputs 1, 2, or 4

Specify the number of input clock sources for the clock control block. You can specify up to four clock inputs.

Clock multiplexing in F-Series and I-Series devices is implemented using soft logic in the core.

Ensure glitch free clock switchover On or Off

Turn on this option to implement a glitch-free switchover when you use multiple clock inputs. You must ensure the currently selected clock is running before switching to another source.

If the selected clock is not running, you cannot switch to the new clock source using the glitch-free switchover implementation.

By default, the clkselect port is set to 00. You must apply a clock to inclk0x to read the values on the clkselect ports.

Turning off this option implements a simple multiplexer logic. For more information about the optimal clock multiplexing design, refer to the Clock Multiplexing section in the Quartus® Prime Pro Edition User Guide: Design Recommendations.

Clock Enable On or Off Turn on this option if you want to gate your clock output with an enable signal. This option disables the option to use clock division.
Clock Enable Type Root Level or Distributed Sector Level Select the clock gates located in the periphery or the gates located in the sector. For more information about the clock gates, refer to the Clock Gating section.
Enable Register Mode Negative Latch or None Specify if the enable signal should be latched.
Clock Divider On or Off Turn on this option if you want to use the clock division block in the periphery.
Clock Divider Output Ports Divide 1x, Divide 1x and 2x, or Divide 1x, 2x and 4x Specify the combination of passing your clock through, dividing your clock by 2, or dividing your clock by 4.