Agilex™ 7 Clocking and PLL User Guide: F-Series and I-Series

ID 683761
Date 4/01/2024
Document Table of Contents

3.7. IP Core Constraints

To implement the IOPLL IP core, you must adhere to the following constraints:

  • Any SDC design constraints referring to the I/O PLL clocks must be listed after the SDC constraints for the IOPLL IP core.
  • Intel recommends reading the SDC for all I/O PLLs first in a design. You can do this by listing the IP before others in the .qsf file.