Agilex™ 7 Clocking and PLL User Guide: F-Series and I-Series

ID 683761
Date 11/28/2024
Public
Document Table of Contents

6.5.2. Output Clock and the Corresponding Data Bit Setting for Clock Gating Reconfiguration

Table 26.  Output Clock and the Corresponding Data Bit Setting for Clock Gating Reconfiguration
Output Clock Data Bus Bit Setting (Binary)
C1 data[0]

Gated = 0'b0

Ungated = 1'b1

C2 data[1]
C3 data[2]
C4 data[3]
C5 data[4]
C6 data[5]
C7 data[6]