Agilex™ 7 Clocking and PLL User Guide: F-Series and I-Series

ID 683761
Date 4/01/2024
Document Table of Contents

6.3.3. Clock Gating Reconfiguration

You can gate (disable) and un-gate (enable) I/O PLL output clock 0 to output clock 7 of the I/O PLL. It is easily done by writing one byte to the IOPLL Reconfig IP core, with one bit corresponding to each of the I/O PLL output clocks.

To perform clock gating reconfiguration, follow these steps:

  1. Set mgmt_address[9:8] to 2’b10 to select clock gating mode and set mgmt_writedata[7:0] to indicate desired output clock to be gated.
  2. To start the clock gating reconfiguration on the I/O PLL, assert the mgmt_write signal for one mgmt_clk cycle.
  3. The gating changes may not come into effect for multiple clock cycles after mgmt_waitrequest has been de-asserted.