Agilex™ 7 Clocking and PLL User Guide: F-Series and I-Series

ID 683761
Date 4/01/2024
Document Table of Contents LVDS Compensation Mode

LVDS compensation mode maintains the same data and clock timing relationship at the pins of the internal serializer/deserializer (SERDES) capture register, except that the clock is inverted (180° phase shift). Thus, LVDS compensation mode ideally compensates for the delay of the LVDS clock network, including the difference in delay between the following two paths:

  • Data pin-to-SERDES capture register
  • Clock input pin-to-SERDES capture register

The output counter must provide the 180° phase shift.

Figure 11. Example of Phase Relationship Between the Clock and Data in LVDS Compensation Mode