Agilex™ 7 Clocking and PLL User Guide: F-Series and I-Series

ID 683761
Date 4/01/2024
Document Table of Contents

6. IOPLL Reconfig Intel® FPGA IP Core

You can use F-Series and I-Series devices to implement phase-locked loop (PLL) reconfiguration and dynamic phase shift for I/O PLLs.

The F-Series and I-Series I/O PLL supports dynamic reconfiguration when the device is in user mode. With the dynamic reconfiguration feature, you can reconfigure the I/O PLL settings in real time. You can change the divide settings of the PLL counters and the PLL bandwidth settings (loop filter setting and charge pump setting) through an Avalon® memory-mapped interface in the IOPLL Reconfig IP core, without the need to reconfigure the entire FPGA. The F-Series and I-Series I/O PLL uses divide counters (N, M, and C counters) and a voltage-controlled oscillator (VCO) to synthesize the desired phase and frequency output.

You can use the IOPLL Reconfig IP core as follows:

  • Memory Initialization File (.mif) streaming reconfiguration
    • Allows the I/O PLL reconfiguration using predefined settings saved in an on-chip ROM. You can store many unique PLL configurations in a single ROM.
    • The .mif file is generated automatically by the IOPLL IP core. Using the generated .mif file during .mif streaming reconfiguration ensures the legality of the new configuration.
    • Intel recommends using this reconfiguration method.
  • Advanced mode reconfiguration
    • This method of reconfiguration is for advanced users. You must ensure the reconfigured PLL settings are within the legal range.
    • Enable the Advanced Reconfiguration option from the IOPLL Reconfig IP core to reconfigure the individual I/O PLL registers.
    • This method is error prone and may lead to the I/O PLL being reconfigured into an illegal configuration if the reconfiguration is done incorrectly.
  • Recalibration of the I/O PLL using .mif
    • Perform recalibration of the I/O PLL without any reconfiguration.
    • Trigger recalibration if the reference clock frequency changes.
  • I/O PLL clock gating
    • Gate and un-gate I/O PLL output clock 0 to output clock 7 of the I/O PLL.

You can perform dynamic phase shift using the IOPLL Reconfig IP core.