AN 813: Hierarchical Partial Reconfiguration over PCI Express* Reference Design: for Intel® Arria® 10 Devices

ID 683730
Date 1/20/2021
Document Table of Contents

1. Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices

Updated for:
Intel® Quartus® Prime Design Suite 20.3
The Hierarchical Partial Reconfiguration (HPR) over PCI Express* ( PCIe* ) reference design demonstrates reconfiguring the FPGA fabric through the PCIe* link in Intel® Arria® 10 devices. This reference design runs on a Linux system with the Intel® Arria® 10 GX FPGA development board. Adapt this reference design to your requirements by implementing the PR region logic using the given template. Run your custom design on this fully functional system that enables communication over PCIe* .

Intel® Arria® 10 devices use the PR over PCIe* solution to reconfigure the device, rather than Configuration via Protocol (CvP) update. Partial reconfiguration allows you to reconfigure a portion of the FPGA dynamically, while the remaining FPGA design continues to function. Create multiple personas for a particular region in your design, without impacting operation in areas outside this region. Partial reconfiguration enables the implementation of more complex FPGA systems.

You can also include multiple parent and child partitions, or create multiple levels of partitions in your design. This hierarchical partial reconfiguration (HPR) flow includes a static region that instantiates the parent PR region, and the parent PR region instantiating the corresponding child PR region. You can perform the same PR region reprogramming for either the child or the parent partition. Reprogramming a child PR region does not affect the parent or the static region. Reprogramming the parent region reprograms the associated child region with the default child persona, without affecting the static region.

Partial reconfiguration provides the following advancements to a flat design:

  • Allows run-time design reconfiguration
  • Increases scalability of the design through time-multiplexing
  • Lowers cost and power consumption through efficient use of board space
  • Supports dynamic time-multiplexing functions in the design
  • Improves initial programming time through smaller bitstreams
  • Reduces system down-time through line upgrades
  • Enables easy system update by allowing remote hardware change