1.1.2. Memory Address Mapping
The Intel Arria 10/Cyclone 10 Hard IP for PCI Express IP connects to the design core through two Avalon® memory mapped master interfaces. These Avalon® memory mapped master interfaces are base address registers (BARs), BAR 2 and BAR 4. BAR 2 connects the PR driver to the following components:
- The Partial Reconfiguration Controller Intel® Arria® 10/Cyclone 10 GX FPGA IP
- The system description ROM
The BAR 4 Avalon® memory map connects to the following components:
- The freeze bridges
- The Partial Reconfiguration Region Controller Intel® FPGA IP
- Up to 8 kilobytes (KB) of memory in the PR region
The following table lists the memory address mapping for the Intel Arria 10/Cyclone 10 Hard IP for PCI Express IP:
|BAR 2||System Description ROM||0x0000_0000||0x0000_0FFF|
|BAR 2||PR IP||0x0000_1000||0x0000_103F|
|BAR 4||PR Region||0x0000_0000||0x0000_FFFF|
|BAR 4||PR Region Controller||0x0001_0000||0x0001_000F|
|BAR 4||DDR4 Calibration Export||0x0001_0010||0x0001_001F|
The External Memory Interfaces Intel® Arria® 10 FPGA IP provides status on DDR4 calibration. During initialization, the External Memory Interfaces Intel® Arria® 10 FPGA IP performs training to reset the DDR4 interface. The EMIF calibration flag reports the training success or the failure to the host. The host takes the necessary action in the event of a DDR4 training failure.
The following table lists the memory address mapping from the External Memory Interfaces Intel® Arria® 10 FPGA IP to the PR logic:
The PR logic accesses the 2 gigabyte (GB) DDR4 memory space using an Avalon® memory mapped master interface.
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