AN 813: Hierarchical Partial Reconfiguration over PCI Express* Reference Design: for Intel® Arria® 10 Devices

ID 683730
Date 1/20/2021
Public
Document Table of Contents

1.1.1. Clocking Scheme

The reference design creates a separate IOPLL Intel® FPGA IP-generated clock. This clock creation decouples the PR logic clocking from both the PCIe* clocking domain that runs at 250 MHz, and the external memory interface (EMIF) clocking domain that runs at 330 MHz. The clock for PR logic is set at 250 MHz. To ease timing closure, modify the parameterization of the IOPLL IP core to a lower clock frequency.