AN 813: Hierarchical Partial Reconfiguration over PCI Express* Reference Design: for Intel® Arria® 10 Devices

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ID 683730
Date 1/20/2021
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Document Table of Contents
Document Table of Contents x
1. Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices
1. Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices x
1.1. Reference Design Overview 1.2. Floorplanning 1.3. Getting Started 1.4. Reference Design Components 1.5. Compiling the Reference Design 1.6. Bringing Up the Reference Design 1.7. Testing the Reference Design 1.8. Extending the Reference Design with Custom Persona 1.9. Reference Design Files 1.10. Document Revision History for AN 813: Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices
1.1. Reference Design Overview x
1.1.1. Clocking Scheme 1.1.2. Memory Address Mapping
1.3. Getting Started x
1.3.1. Hardware and Software Requirements 1.3.2. Installing the Intel® Arria® 10 GX FPGA Development Kit 1.3.3. Installing the Linux Driver
1.4. Reference Design Components x
1.4.1. BSP Top
1.4.1. BSP Top x
1.4.1.1. Intel Arria 10/Cyclone 10 Hard IP for PCI Express IP 1.4.1.2. External Memory Interfaces Intel® Arria® 10 FPGA IP 1.4.1.3. Design Top
1.4.1.3. Design Top x
1.4.1.3.1. Global Reset Logic 1.4.1.3.2. PR Region Wrapper 1.4.1.3.3. Parent PR Region 1.4.1.3.4. Partial Reconfiguration Region Controller Intel® FPGA IP 1.4.1.3.5. Partial Reconfiguration Logic
1.7. Testing the Reference Design x
1.7.1. program_fpga_jtag 1.7.2. fpga-configure example_host_uio
example_host_uio x
1.7.3.1. Compiling the Example Applications 1.7.3.2. Programming the Design Using Example Applications
1. Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices

1.7.1. program_fpga_jtag

Use the program_fpga_jtag script to program the entire device (full-chip programming) without any requirement for reboot.

program_fpga_jtag performs the following functions:

  • Uses the Intel® Quartus® Prime Programmer to program the device.
  • Accepts an SRAM Object File (.sof) and configures the target device over a JTAG interface.
  • Communicates with the driver to perform the following functions:
    • Disable upstream AER (advanced error reporting)
    • Save state
    • Restore AER
    • Restore state
Table 7.   program_fpga_jtag Command-Line Options
Option Description
-f=, --file=[<filename>]

Specifies the .sof file name.

-c= ,--cable=[<cable number>]

Specifies the programmer cable.
-i, --index

Specifies the index of the target device in the JTAG chain.
-h, --help

Provides help for program_fpga_jtag script.

Note: Use the following command to the obtain the device index: 
/sbin/lspci -d1172:
For example, consider that the command returns the following output: 
03:00.0 Class ea00: Intel FPGA Device 5052 (rev 01)
The first value is the device index. Prepend 0000 to this value. In this case, your device index is 0000.03:00.0.
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