AN 813: Hierarchical Partial Reconfiguration over PCI Express* Reference Design: for Intel® Arria® 10 Devices

ID 683730
Date 1/20/2021
Document Table of Contents Design Top

This component forms the core of the design, and includes the following:
  • Reset logic
  • PR region
  • Partial Reconfiguration Controller Intel® Arria® 10/Cyclone 10 GX FPGA IP
  • Clock crossing and pipe-lining for Avalon® memory mapped transactions
  • System description ROM
  • PLL