AN 813: Hierarchical Partial Reconfiguration over PCI Express* Reference Design: for Intel® Arria® 10 Devices

ID 683730
Date 1/20/2021
Document Table of Contents

1.6. Bringing Up the Reference Design

The reference design is available in the following location:

To access the reference design, navigate to the ref_designs sub-folder. Copy the a10_pcie_devkit_cvp_hpr folder to the home directory in your Linux system.

To bring up the reference design on the board:
  1. Plug-in the Intel® Arria® 10 GX FPGA development board to an available PCIe* slot in your host machine.
  2. Connect the host machine's ATX auxiliary power connector to the 12 V ATX input J4 of the development board.
  3. Power-up the host machine.
  4. Verify the micro-USB cable connection to the FPGA development board. Ensure that no other applications that use the JTAG chain are running.
  5. Navigate to the a10_pcie_devkit_cvp_hpr/software/installation folder in your system.
  6. To overwrite the existing factory image on the board with the reference design, execute the script.
  7. Pass the JTAG cable number of your connected device as an argument to the script (for example, perl 1).
    Running this script configures the device with the contents of the flash.pof file. This parallel object file comes directly from the a10_pcie_devkit_cvp.sof file present in the project directory. The flash.pof file acts as the base image for the reference design.
    Note: Ensure successful compilation of the design before running this script.
  8. Power-cycle the host machine.