AN 813: Hierarchical Partial Reconfiguration over PCI Express* Reference Design: for Intel® Arria® 10 Devices

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ID 683730
Date 1/20/2021
Public
Document Table of Contents
Document Table of Contents x
1. Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices
1. Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices x
1.1. Reference Design Overview 1.2. Floorplanning 1.3. Getting Started 1.4. Reference Design Components 1.5. Compiling the Reference Design 1.6. Bringing Up the Reference Design 1.7. Testing the Reference Design 1.8. Extending the Reference Design with Custom Persona 1.9. Reference Design Files 1.10. Document Revision History for AN 813: Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices
1.1. Reference Design Overview x
1.1.1. Clocking Scheme 1.1.2. Memory Address Mapping
1.3. Getting Started x
1.3.1. Hardware and Software Requirements 1.3.2. Installing the Intel® Arria® 10 GX FPGA Development Kit 1.3.3. Installing the Linux Driver
1.4. Reference Design Components x
1.4.1. BSP Top
1.4.1. BSP Top x
1.4.1.1. Intel Arria 10/Cyclone 10 Hard IP for PCI Express IP 1.4.1.2. External Memory Interfaces Intel® Arria® 10 FPGA IP 1.4.1.3. Design Top
1.4.1.3. Design Top x
1.4.1.3.1. Global Reset Logic 1.4.1.3.2. PR Region Wrapper 1.4.1.3.3. Parent PR Region 1.4.1.3.4. Partial Reconfiguration Region Controller Intel® FPGA IP 1.4.1.3.5. Partial Reconfiguration Logic
1.7. Testing the Reference Design x
1.7.1. program_fpga_jtag 1.7.2. fpga-configure example_host_uio
example_host_uio x
1.7.3.1. Compiling the Example Applications 1.7.3.2. Programming the Design Using Example Applications
1. Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices

1.4.1.1. Intel Arria 10/Cyclone 10 Hard IP for PCI Express IP

Instantiate the Intel Arria 10/Cyclone 10 Hard IP for PCI Express IP as part of a Platform Designer system. The Intel Arria 10/Cyclone 10 Hard IP for PCI Express IP is Gen3x8 with a 256-bit interface, running at 250 MHz.

The following table provides information on the PCI Express* IP parameters that the reference design uses that are different from the default settings:

Table 3.   Intel Arria 10/Cyclone 10 Hard IP for PCI Express IP Configuration
Tab Parameter Value
System Settings Application interface type Avalon-MM with DMA
Hard IP mode Gen3:x8, Interface: 256-bit, 250 MHz
Port type Native endpoint
RX buffer credit allocation for received requests vs completions Low
Avalon-MM Settings Enable control register access (CRA) Avalon-MM slave port Disable
Base Address Registers - BAR2 Type 32-bit non-prefetchable memory
Base Address Registers - BAR4 Type 32-bit non-prefetchable memory
Device Identification Registers Vendor ID 0x00001172
Device ID 0x00005052
Revision ID 0x00000001
Class code 0x00ea0001
Subsystem Vendor ID 0x00001172
Subsystem Device ID 0x00000001
PCI Express/PCI Capabilities - Device Maximum payload size 256 Bytes
Configuration, Debug, and Extension Options Enable Intel® Arria® 10 GX FPGA Development Kit Connection Enable
PHY Characteristics Requested equalization far-end TX preset Preset 9
Level Two Title