AN 813: Hierarchical Partial Reconfiguration over PCI Express* Reference Design: for Intel® Arria® 10 Devices

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ID 683730
Date 1/20/2021
Public
Document Table of Contents
Document Table of Contents x
1. Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices
1. Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices x
1.1. Reference Design Overview 1.2. Floorplanning 1.3. Getting Started 1.4. Reference Design Components 1.5. Compiling the Reference Design 1.6. Bringing Up the Reference Design 1.7. Testing the Reference Design 1.8. Extending the Reference Design with Custom Persona 1.9. Reference Design Files 1.10. Document Revision History for AN 813: Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices
1.1. Reference Design Overview x
1.1.1. Clocking Scheme 1.1.2. Memory Address Mapping
1.3. Getting Started x
1.3.1. Hardware and Software Requirements 1.3.2. Installing the Intel® Arria® 10 GX FPGA Development Kit 1.3.3. Installing the Linux Driver
1.4. Reference Design Components x
1.4.1. BSP Top
1.4.1. BSP Top x
1.4.1.1. Intel Arria 10/Cyclone 10 Hard IP for PCI Express IP 1.4.1.2. External Memory Interfaces Intel® Arria® 10 FPGA IP 1.4.1.3. Design Top
1.4.1.3. Design Top x
1.4.1.3.1. Global Reset Logic 1.4.1.3.2. PR Region Wrapper 1.4.1.3.3. Parent PR Region 1.4.1.3.4. Partial Reconfiguration Region Controller Intel® FPGA IP 1.4.1.3.5. Partial Reconfiguration Logic
1.7. Testing the Reference Design x
1.7.1. program_fpga_jtag 1.7.2. fpga-configure example_host_uio
example_host_uio x
1.7.3.1. Compiling the Example Applications 1.7.3.2. Programming the Design Using Example Applications
1. Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices

1.10. Document Revision History for AN 813: Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices

Document Version Intel® Quartus® Prime Version Changes
2021.01.20 20.3
  • Updated supported version number on cover and Hardware and Software Requirements topic.
  • Added new step 1 to Compiling the Reference Design topic.
  • Added new step 7 to Compiling the Reference Design topic.
  • Removed statement about "new" simplified flow.
  • Updated throughout for latest style and legal conventions.
2018.09.24 18.1

  • Updated the Compiling the Reference Design to eliminate the need for manual export of finalized snapshot of the static region.

  • Other minor text edits
2018.07.03 18.0

Updated the Compiling the Reference Design with the correct command for .qdb file export.

2018.05.07 18.0
  • Compilation flow change
  • Other minor text edits
2017.11.06 17.1
  • Updated the Hardware and Software Requirements section with additional reference design requirements
  • Updated the Installing the Linux Driver section with detailed instructions on installing the open source Linux driver
  • Version update
  • Minor text edits
2017.05.22 17.0 Initial Release
Level Two Title