OCT Intel® FPGA IP User Guide

ID 683708
Date 7/03/2019

User Mode OCT

User mode OCT operates the same way as power-up OCT mode, with the addition of user controllability.
Figure 6. FSM SignalsThis figure shows a finite state machine (FSM) in the core controls the dedicated user signals on the OCT block. The FSM ensures that the OCT block calibrates or sends controlling code words as per your request.

The Fitter does not infer a user-mode OCT. If you want your OCT block to use the user mode OCT feature, you must generate the OCT IP. However, because of hardware limitations, you can only use one OCT IP in user mode OCT in your design.

Note: A single OCT IP can control up to 12 OCT blocks.

The FSM provides the following signals:

  • clock
  • reset
  • s2pload
  • calibration_busy
  • calibration_shift_busy
  • calibration_request
Note: These signals are only available in user-mode and not power-up mode.

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