OCT Intel® FPGA IP User Guide

ID 683708
Date 7/03/2019

OCT Intel® FPGA IP Functional Description

To meet DDR memory specification, Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX devices support on-chip series termination (RS OCT) and on-chip parallel termination (RT OCT) for single-ended I/O standards. OCT can be supported on any I/O bank. The VCCIO must be compatible for all I/Os in a given bank.

In an Intel® Stratix® 10, Intel® Arria® 10, or Intel® Cyclone® 10 GX device, there is one OCT block in each I/O bank. Each OCT block requires an association with an external 240 Ω reference resistor through an RZQ pin.

The RZQ pin shares the same VCCIO supply with the I/O bank where the pin is located. An RZQ pin is a dual function I/O pin that you can use as a regular I/O if you do not use OCT calibration. When you use the RZQ pin for OCT calibration, the RZQ pin connects the OCT block to ground through an external 240 Ω resistor.

The following figures show how OCTs are connected in a single I/O column (in a daisy chain). An OCT can calibrate an I/O belonging to any bank, provided that the bank is in the same column and meets the voltage requirements. Because there are no connections between columns, OCT can only be shared if the pins belong to the same I/O column of the OCT.

Figure 3.  OCT Bank-to-Bank Connections

Figure 4. I/O Columns in Intel® Quartus® Prime Pin PlannerThis figure is an example. The layout varies between different Intel® Stratix® 10, Intel® Arria® 10, or Intel® Cyclone® 10 GX devices.