OCT Intel® FPGA IP User Guide

ID 683708
Date 7/03/2019
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OCT Intel® FPGA IP Design Example

The OCT IP can generate a design example that matches the same configuration chosen for the IP.

The design example is a simple design that does not target any specific application. You can use the design example as a reference on how to instantiate the IP.

To generate the design example files, turn on the Generate Example Design option in the Generation dialog box during IP generation.

Note: The OCT IP does not support VHDL generation.
  • The software generates the <instance>_example_design directory along with the IP, where <instance> is the name of your IP.
  • The <instance>_example_design directory contains the make_qii_design.tcl scripts.
Note: The .qsys files are for internal use during design example generation only. You cannot edit the files.