Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX devices have the following termination-related Intel® Quartus® Prime settings file (.qsf) assignments:
The input/output termination assignment specifies the termination value in ohm on the pin in question.
To enable the series/parallel termination ports, include these assignments, which specify the series and parallel termination values for the pins.
Make sure to connect the seriesterminationcontrol and parallelterminationcontrol ports from the OCT Intel® FPGA IP to the GPIO Intel® FPGA IP.
Directs the Fitter to make the proper connection from the desired OCT block to the specified pins. This assignment is useful when I/O buffers are not explicitly instantiated and you need to associate the pins with a specific OCT block.
This assignment is supported in Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX devices only. This assignment creates an OCT IP without modifying the RTL.
The Fitter searches for the rzq pin name in the netlist. If the pin does not exist, the Fitter creates the pin name along with the OCT IP and its corresponding connections. This allows you to create a group of pins to be calibrated by an existing or non-existing OCT and the Fitter ensures the legality of the design.
Termination can exist on input and output buffers, and sometimes simultaneously.
There are two methods to associate pin groups with an OCT block:
- Use a .qsf assignment to indicate which pin (bus) is associated with which OCT block. You can use the TERMINATION_CONTROL_BLOCK or RZQ_GROUPassignment. The former assignment associates a pin with an OCT instantiated in the RTL while the latter associates the pin with a newly created OCT without modifying the RTL.
- Instantiate the I/O buffer primitives at the top level and connect them to the appropriate OCT blocks.