OCT Intel® FPGA IP User Guide

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ID 683708
Date 7/03/2019
Public
Document Table of Contents
Document Table of Contents x
OCT Intel® FPGA IP User Guide
OCT Intel® FPGA IP User Guide x
OCT Intel® FPGA IP Features OCT Intel® FPGA IP Overview OCT Intel® FPGA IP Functional Description OCT Intel® FPGA IP Design Example OCT Intel® FPGA IP References OCT Intel® FPGA IP User Guide Archives Document Revision History for OCT Intel® FPGA IP User Guide
OCT Intel® FPGA IP Overview x
RZQ Pin OCT Block OCT Logic
OCT Intel® FPGA IP Functional Description x
Power-Up Mode Interfaces User Mode OCT
User Mode OCT x
Core FSM
OCT Intel® FPGA IP Design Example x
Generating the Intel® Quartus® Prime Design Example
OCT Intel® FPGA IP References x
OCT Intel® FPGA IP Parameter Settings OCT Intel® FPGA IP Signals QSF Assignments IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices
IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices x
Migrating Your ALTOCT IP to the OCT Intel® FPGA IP
OCT Intel® FPGA IP User Guide

IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices

The IP migration flow allows you to migrate the ALTOCT IP of Arria® V, Cyclone® V, and Stratix® V devices to the OCT Intel® FPGA IP of Intel® Stratix® 10, Intel® Arria® 10, or Intel® Cyclone® 10 GX devices.

The IP migration flow configures the OCT IP to match the settings of the ALTOCT IP, allowing you to regenerate the IP.

Note: This IP supports the IP migration flow in single OCT calibration mode only. If you are using double or POD calibration mode, you do not need to migrate the IP.
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