OCT Intel® FPGA IP Signals
|rzqin||Input||Input connection from RZQ pad to the OCT block. RZQ pad is connected to an external resistance. The OCT block uses impedance connected to the rzqin port as a reference to generate the calibration code.
This signal is available for power-up and user modes.
|clock||Input||Input clock for user mode OCT. The clock must be 20 MHz or less.|
|reset||Input||Input reset signal. Reset is synchronous.|
|calibration_request||Input||Input vector for [NUMBER_OF_OCT:0]. Every bit corresponds to an OCT block. When a bit is set to 1, the corresponding OCT calibrates, then serially shift the code word into the termination logic block. The request has to be held for two clock cycles. Due to hardware limitations, you must wait until the calibration_shift_busy vector to be zero until another request is issued; otherwise your request will not be processed.|
|calibration_shift_busy||Output||Output vector for [NUMBER_OF_OCT:0] indicating which OCT block is currently working on calibration and shifting termination codes to the termination logic block. When a bit is 1, it indicates that an OCT block is calibrating and shifting the code word to the termination logic block.|
|calibration_busy||Output||Output vector for [NUMBER_OF_OCT:0] indicating which OCT block is currently working on calibration. When a bit is 1, it indicates that an OCT block is calibrating|
|oct_<x>_series_termination control[15:0]||Output||16-bit output signal, with <x> ranging from 0 to 11. This signal connects to the seriesterminationcontrol port on the input/output buffer. This port sends the series termination code that calibrates Rs.|
|oct_<x>_parallel_termination_control[15:0]||Output||16-bit output signal, with <x> ranging from 0 to 11. This signal connects to the parallelterminationcontrol port on the input/output buffer. This port sends the parallel termination code that calibrates Rt.|
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