OCT Intel® FPGA IP User Guide

ID 683708
Date 7/03/2019

OCT Logic

The OCT block sends the calibration code words serially to the OCT logic through the ser_data ports.

The enser signal, when triggered, specifies from which OCT block to read the calibration code words. The calibration code words are then buffered into the serial-to-parallel shift logic. After that, the s2pload signal automatically asserts to send the calibration code words in parallel to the I/O buffers.

The calibration code words activate or deactivate the transistors in the I/O block, which will emulate series or parallel resistance to match the impedance.

Figure 2. Internals of OCT Logic

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