OCT Intel® FPGA IP User Guide

ID 683708
Date 7/03/2019
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Core FSM

Figure 7. FSM Flow

Table 2.  FSM States
State Description
IDLE When you set the calibration_request vector, the FSM moves from IDLE state to CAL state. Keep the calibration_request vector at its value for two clock cycles. After two clock cycles, the FSM contains a copy of the vector. You must reset the vector to avoid reinitiating the calibration process.
CAL During this state, the FSM checks which bits in the calibration_request vector were asserted and services them. The corresponding OCT blocks starts the calibration process that takes around 2,000 clock cycles to complete. After calibration completes, the calibration_busy signal is released.
Check Mask bit The FSM checks each bit in the vector if the bit is set or not.
Shift Mask bit This state simply loops over all the bits in the vector until it hits a 1.
Series Shift This state serially sends the termination code from the OCT block to the termination logic. It takes 32 cycles to complete the transfer. After each transfer, the FSM check for any pending bits in the vector and services them accordingly.
Update Pending Bit The pending register holds bits that corresponds to every OCT block in the OCT Intel® FPGA IP. This state updates the pending register by resetting the serviced request.

When the calibration_shift_busy signal is deasserted, you can assert s2pload automatically asserts to transfer the new termination codes into the buffers. The s2pload signal asserts for at least 25 ns.

Because of hardware limitations, you cannot request another calibration until all bits in calibration_shift_busy vector are low.