Parallel Flash Loader Intel® FPGA IP User Guide

ID 683698
Date 4/03/2023
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1.4.3. Simulating PFL Design

You can simulate the behavior of the PFL IP core with the ModelSim®- Intel® FPGA software as if it configures an FPGA. This section provides guidelines on the PFL simulation for FPGA configuration.
Note: You can perform PFL simulation using gate-level simulation, which is based on functional netlist. PFL simulation does not support RTL simulation. PFL simulation does not reflect the true behavior of the hardware. Intel® certifies the PFL IP core based on actual hardware testing, and not through PFL simulation.
Table 9.  Files Required for PFL Simulation in the ModelSim- Intel® FPGA Software
File/Library Description
.vo or .vho The Verilog HDL or VHDL output file of the PFL IP core.
.sdo The Standard Delay Format Output file (.sdo) of the PFL IP core.
Simulation libraries:
  • altera
  • altera_mf
  • maxii
  • maxv
The precompiled library files for Intel® FPGA IP core primitives and Intel® CPLDs in the ModelSim- Intel® FPGA software.
Test bench Test bench file to establish the interface between the PFL IP core and the flash memory device.
Flash simulation model files The simulation model files for the flash memory devices in the PS or FPP configuration. For the flash simulation model file for each flash memory device, refer to the respective flash memory device manufacturer.