1.1. Features 1.2. Device Support 1.3. Functional Description 1.4. Using the PFL IP Core 1.5. PFL IP Core In Embedded Systems 1.6. Third-party Programmer Support 1.7. Parameters 1.8. Signals 1.9. Specifications 1.10. Parallel Flash Loader Intel® FPGA IP User Guide Archives 1.11. Document Revision History for the Parallel Flash Loader Intel® FPGA IP User Guide
1.4.1. Converting .sof Files to a .pof 1.4.2. Constraining PFL Timing 1.4.3. Simulating PFL Design 1.4.4. Programming Intel® CPLDs and Flash Memory Devices 1.4.5. Defining New CFI Flash Device 1.4.6. Programming Multiple Flash Memory Devices 1.4.7. Creating Jam Files for Intel® CPLDs and Flash Memory Device Programming
1.3.3. Mapping PFL and Flash Address
The address connections between the PFL IP core and the flash memory device vary depending on the flash memory device vendor and data bus width.
Figure 7. Micron J3 Flash Memory in 8-Bit ModeThe address connection between the PFL IP core and the flash memory device are the same.
Figure 8. Micron J3, P30, and P33 Flash Memories in 16-Bit ModeThe flash memory addresses in Micron J3, P30, and P33 16-bit flash memory shift one bit down in comparison with the flash addresses in the PFL IP core. The flash address in the Micron J3, P30, and P33 flash memory starts from bit 1 instead of bit 0.
Figure 9. Cypress and Micron M28, M29, and MT28EW Flash Memory in 8-Bit ModeThe flash memory addresses in Cypress 8-bit flash shifts one bit up. Address bit 0 of the PFL IP core connects to data pin D15 of the flash memory.
Figure 10. Cypress and Micron M28, M29, and MT28EW Flash Memory in 16-Bit ModeThe address bit numbers in the PFL IP core and the flash memory device are the same.
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