||Specifies the operating mode of flash programming and FPGA configuration control in one IP core or separate these functions into individual blocks and functionality.|
|Targeted flash device||
||Specifies the flash memory device connected to the PFL IP core.|
|Tri-state flash bus||On or Off||Allows the PFL IP core to tri-state all pins interfacing with the flash memory device when the PFL IP core does not require an access to the flash memory.|
|Number of flash devices used||
||Specifies the number of flash memory devices connected to the PFL IP core.|
|Largest flash density||
Specifies the density of the flash memory device to be programmed or used for FPGA configuration. If you have more than one flash memory device connected to the PFL IP core, specify the largest flash memory device density.
For dual mode CFI and NAND flash devices, select the density that is equivalent to the sum of the density of two CFI flashes. For example, if you use two 512-Mb CFI flashes, you must select CFI 1 Gbit. (Available only if you select CFI Parallel Flash or NAND Flash.)
|Flash interface data width||
Specifies the flash data width in bits. The flash data width depends on the flash memory device you use. For multiple flash memory device support, the data width must be the same for all connected flash memory devices.
For CFI flash, select the flash data width that is equivalent to the sum of the data width of two CFI flashes. For example, if you are targeting dual P30 or P33 solution, you must select 32 bits because each CFI flash data width is 16 bits. (Available only if you select CFI Parallel Flash or NAND Flash.)
|User control flash_nreset pin||On or Off||
Creates a flash_nreset pin in the PFL IP core to connect to the reset pin of the flash memory device. A low signal resets the flash memory device. In burst mode, this pin is available by default.
When using a GL flash device, connect this pin to the RESET# pin of the flash device. (Available only if you select CFI Parallel Flash.)
|Quad SPI flash device manufacturer||
||Specifies the device manufacturer of the quad SPI flash. (Available only if you select Quad SPI Flash.)|
|Quad SPI flash device density||8 Mbit–256 Mbit||Specifies the density of the quad SPI flash to be programmed or used for FPGA configuration. (Available only if you select Quad SPI Flash.)|
|Byte address for reserved block area||—||
Specifies the start address of the reserved block area for bad block management.
NAND flash memory may contain bad blocks that contain one or more invalid bits. The reserve blocks replace any bad blocks that the PFL IP core encounters. Intel recommends that you reserve a minimum of 2% of the total block. (Available only if you select NAND Flash.)
|On-die ECC support||On or Off||
Enables the support for on-die ECC. Certain NAND flash memory devices has on-die ECC. Allows the PFL IP core to use the on-die ECC of the flash memory device.
Turning off this option allows the PFL IP core to generate its own ECC engine. (Available only if you select NAND Flash.)
|Flash programming IP optimization||Area, Speed||Specifies the flash programming IP optimization. If you optimize the PFL IP core for speed, the flash programming time is shorter but the IP core uses more LEs. If you optimize the PFL IP core for area, the IP core uses less LEs, but the flash programming time is longer. (Available only if you select CFI Parallel Flash.)|
|FIFO size||16, 32||Specifies the FIFO size if you select Speed for flash programming IP optimization. The PFL IP core uses additional LEs to implement FIFO as temporary storage for programming data during flash programming. With a larger FIFO size, programming time is shorter. (Available only if you select CFI Parallel Flash.)|
|Add Block-CRC verification acceleration support||On or Off||Adds a block to accelerate verification. (Available only if you select CFI Parallel Flash.)|
|External clock frequency||—||Specifies the user-supplied clock frequency for the IP core to configure the FPGA. The clock frequency must not exceed two times the maximum clock (DCLK) frequency acceptable by the FPGA for configuration. The PFL IP core can divide the frequency of the input clock maximum by two.|
|Flash access time||—||
Specifies the access time of the flash. You can get the maximum access time that a flash memory device requires from the flash datasheet. Intel recommends specifying a flash access time that is the same as or longer than the required time.
For CFI parallel flash, the unit is in ns and for NAND flash, the unit is in us. NAND flash uses page instead of byte, and requires more access time. This option is disabled for quad SPI flash.
|Option bits byte address||—||
Specifies the start address in which the option bits are stored in the flash memory. The start address must reside on an 8-KB boundary.
See related for more information about option bits.
|FPGA configuration scheme||
||Select the FPGA configuration scheme. The default FPP is FPP ×8. If you are using Stratix V devices, two additional FPP mode is available: FPP ×16 and FPP ×32.|
|Configuration failure response options||Halt, Retry same page, or Retry from fixed address||Configuration behavior after configuration failure.
|Byte address to retry from on configuration failure||—||If you select Retry from fixed address for configuration failure option, this option specifies the flash address for the PFL IP core to read from the reconfiguration for a configuration failure.|
|Include input to force reconfiguration||On or Off||Includes an optional reconfiguration input pin (pfl_nreconfigure) to enable a reconfiguration of the FPGA.|
|Watchdog timer||On or Off||Enables a watchdog timer for remote system upgrade support. Turning on this option enables the pfl_reset_watchdog input pin and pfl_watchdog_error output pin, and specifies the time period before the watchdog timer times out. This watchdog timer is a time counter which runs at the pfl_clk frequency.|
|Time period before the watchdog timer times out||—||Specifies the time out period of the watchdog timer. The default time out period is 100 ms|
|Ratio between input clock and DCLK output clock||1, 2, 4, or 8||Specifies the ratio between the input clock and DCLK.
|Use advance read mode||
||An option to improve the overall flash access time for the read process during the FPGA configuration.
|Enhanced bitstream decompression||
||Select to enable or disable the enhanced bitstream decompression block.