Parallel Flash Loader Intel® FPGA IP User Guide

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Date 4/03/2023
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Document Table of Contents
Document Table of Contents x
1. Parallel Flash Loader Intel® FPGA IP User Guide
1. Parallel Flash Loader Intel® FPGA IP User Guide x
1.1. Features 1.2. Device Support 1.3. Functional Description 1.4. Using the PFL IP Core 1.5. PFL IP Core In Embedded Systems 1.6. Third-party Programmer Support 1.7. Parameters 1.8. Signals 1.9. Specifications 1.10. Parallel Flash Loader Intel® FPGA IP User Guide Archives 1.11. Document Revision History for the Parallel Flash Loader Intel® FPGA IP User Guide
1.2. Device Support x
1.2.1. Supported Flash Memory Devices 1.2.2. Supported Schemes and Features
1.3. Functional Description x
1.3.1. Programming Flash Memory 1.3.2. Controlling Intel® FPGA Configuration from Flash Memory 1.3.3. Mapping PFL and Flash Address 1.3.4. Implementing Page in the Flash .pof 1.3.5. Using Enhanced Bitstream Compression and Decompression 1.3.6. Using Remote System Upgrade
1.3.1. Programming Flash Memory x
1.3.1.1. Programming CFI Flash 1.3.1.2. Programming Quad SPI Flash 1.3.1.3. Programming NAND Flash
1.3.4. Implementing Page in the Flash .pof x
1.3.4.1. Storing Option Bits
1.3.6. Using Remote System Upgrade x
1.3.6.1. Remote System Upgrade State Machine in the PFL IP Core 1.3.6.2. Implementing Remote System Upgrade with the PFL IP Core 1.3.6.3. User Watchdog Timer
1.4. Using the PFL IP Core x
1.4.1. Converting .sof Files to a .pof 1.4.2. Constraining PFL Timing 1.4.3. Simulating PFL Design 1.4.4. Programming Intel® CPLDs and Flash Memory Devices 1.4.5. Defining New CFI Flash Device 1.4.6. Programming Multiple Flash Memory Devices 1.4.7. Creating Jam Files for Intel® CPLDs and Flash Memory Device Programming
1.4.2. Constraining PFL Timing x
1.4.2.1. Constraining Clock Signal 1.4.2.2. Constraining Synchronous Input and Output Ports 1.4.2.3. Constraining Asynchronous Input and Output Ports, and Bidirectional Synchronous Ports 1.4.2.4. Summary of PFL Timing Constraints
1.4.3. Simulating PFL Design x
1.4.3.1. Creating a Test Bench File for PFL Simulation 1.4.3.2. Performing PFL Simulation in the ModelSim- Intel® FPGA Software 1.4.3.3. Performing PFL Simulation for FPGA Configuration
1.4.4. Programming Intel® CPLDs and Flash Memory Devices x
1.4.4.1. Programming Intel® CPLDs and Flash Memory Devices Separately
1.9. Specifications x
1.9.1. Configuration Time Calculation Examples
1. Parallel Flash Loader Intel® FPGA IP User Guide

1.3.4.1. Storing Option Bits

The PFL IP core requires you to allocate space in the flash memory device for option bits. The option bits sector contains information about the start address for each page, the .pof version used for flash programming, and the Page-Valid bits. You must specify the options bits sector address in the flash memory device when converting the .sof files to a .pof and creating a PFL design.
Table 4.  Option Bits Sector FormatOffset address 0x80 stores the .pof version required for programming flash memory. This .pof version applies to all eight pages of the configuration data. The PFL IP core requires the .pof version to perform a successful FPGA configuration process.
Sector Offset Value
0x00–0x03 Page 0 start address
0x04–0x07 Page 1 start address
0x08–0x0B Page 2 start address
0x0C–0x0F Page 3 start address
0x10–0x13 Page 4 start address
0x14–0x17 Page 5 start address
0x18–0x1B Page 6 start address
0x1C–0x1F Page 7 start address
0x20–0x7F Reserved
0x80 11 .pof version
0x81–0xFF Reserved

The Intel® Quartus® Prime Convert Programming File tool generates the information for the .pof version when you convert the .sof files to .pof files.

The value for the .pof version generated by the Intel® Quartus® Prime software 0x03. However, if you turn on the enhanced bitstream-compression feature, the value for the .pof version is 0x04.

CAUTION:
Do not overwrite any information in the option bits sector to prevent the PFL IP core from malfunctioning, and always store the option bits in unused addresses in the flash memory device.
Figure 11. Implementing Page Mode and Option Bits in the CFI Flash Memory Device
  • The end address depends on the density of the flash memory device. For the address range for devices with different densities, refer Byte Address Range table.
  • You must specify the byte address for the option bits sector.
Figure 12. Page Start Address, End Address, and Page-Valid Bit Stored as Option BitsBits 0 to 12 for the page start address are set to zero and are not stored as option bits. The Page-Valid bits indicate whether each page is successfully programmed. The PFL IP core programs the Page-Valid bits after successfully programming the pages.
Table 5.  Byte Address Range for CFI Flash Memory Devices with Different Densities
CFI Device (Megabit) Address Range
8 0x0000000–0x00FFFFF
16 0x0000000–0x01FFFFF
32 0x0000000–0x03FFFFF
64 0x0000000–0x07FFFFF
128 0x0000000–0x0FFFFFF
256 0x0000000–0x1FFFFFF
512 0x0000000–0x3FFFFFF
1024 0x0000000–0x7FFFFFF
11 .pof version occupies only one byte in the option bits sector.
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