Parallel Flash Loader Intel® FPGA IP User Guide

ID 683698
Date 4/03/2023
Document Table of Contents Performing PFL Simulation for FPGA Configuration

Before beginning the FPGA configuration, the PFL IP core reads the option bits stored in the option bits sector to obtain information about the .pof version used for flash programming, the start and end address of each page of the configuration image stored in the flash, and the Page-Valid bit.

In this simulation example, the start and end addresses of the option bits sector are 0×800000 and 0×800080, respectively. The PFL IP core first reads from the final address, which is 0×800080, to obtain the .pof version information. Because fpga_pgm[2..0] is set to 000, the PFL IP core reads from address 0×800000 to address 0×800003 to get the start and end address of page 0 and the Page-Valid bit. The LSB in address 0×800000 is the Page-Valid bit.

The Page-Valid bit must be 0 for the PFL IP core to proceed with FPGA configuration. While the PFL IP core reads from the flash, it asserts the active-low flash_nce and flash_noe signals, and asserts the active-high pfl_flash_access_request signal.

Note: Before you perform the device configuration simulation, ensure that the PFL IP core receives the correct option bits address and associated values to guarantee correct simulation output.
Figure 20. Simulation Before ConfigurationFigure shows the simulation when the PFL IP core reads the option bits from the flash memory device before configuration starts.

After reading the option bits for page 0, the PFL IP core waits for a period of time before the configuration starts. The flash_data remains at 0×ZZ within this period. Configuration starts when the fpga_dclk starts to toggle. During configuration, the PFL IP core asserts the flash_nce and flash_noe signals low, and the pfl_flash_access_request signal high.

Figure 21. Simulation When FPGA Configuration Starts

The FPGA configuration continues until the fpga_conf_done signal is asserted high, which indicates the configuration is complete. After the configuration process completes, the PFL IP core pulls the flash_nce and flash_noe signals high and the pfl_flash_access_request signal low to indicate the configuration data is no longer being read from the flash memory device.