22.214.171.124. Constraining Synchronous Input and Output Ports
The signal delay from FPGA or flash memory device to the PFL synchronous input port is specified by set_input_delay. The delay calculation is:
Input delay value = Board delay from FPGA or flash output port to the PFL input port + TCO of the FPGA or flash memory device
The signal delay from PFL synchronous output port to FPGA or flash memory device is specified by set_output_delay. The delay calculation is:
Output delay value = Board delay from the PFL output port to the FPGA or flash input port + TSU / -TDH of FPGA or flash device.
To constrain the synchronous input and output signals in the Timing Analyzer, follow these steps:
- Run full compilation for the PFL design. Ensure that the timing analysis tool is set to Timing Analyzer.
- After full compilation completes, on the Tools menu, select Timing Analyzer to launch the Timing Analyzer window.
- In the Tasks list, under Diagnostic, click Report Unconstrained Paths to view the list of unconstrained parts and ports of the PFL design.
- In the Report list, under the Unconstrained Paths category, select Setup Analysis, and then click Unconstrained Input Port Paths.
- Right-click each synchronous input or output port in the From list or To list and select set_input_delay for the input port or set_output_delay for the output port, then specify the input delay or output delay value.