Parallel Flash Loader Intel® FPGA IP User Guide

ID 683698
Date 4/03/2023
Document Table of Contents Performing PFL Simulation in the ModelSim- Intel® FPGA Software

To perform PFL simulation in the ModelSim- Intel® FPGA software, you must specify the .sdo or load the ModelSim precompiled libraries listed in Files Required for PFL Simulation in the ModelSim- Intel® FPGA Software table. Alternatively, you can generate the .vo, .sdo and Modelsim precompiled libraries through NativeLink feature in Intel® Quartus® Prime.

To set up the simulation using NativeLink and perform ModelSim simulation, follow these steps:

  1. On the Assignments menu, click Settings to open the Settings dialog box and then under EDA Tool Settings, click Simulation.
  2. Verify that ModelSim- Intel® FPGA is selected in the Tool name field and click OK.
  3. To run simulation right after design compilation, turn on theRun gate-level simulation automatically after compilation option.
  4. Specify Format for output netlist, Time scale, and Output directory.
  5. Under NativeLink settings, select Compile test bench then click Test Benches.
  6. In the Test Bench dialog box appears, click New. Fill in the settings, insert simulation model files for the flash memory devices and test bench.
    Figure 19. Test Bench Settings
  7. After settings are done, compile the design and the simulation starts automatically.