Parallel Flash Loader Intel® FPGA IP User Guide

ID 683698
Date 4/03/2023
Document Table of Contents Remote System Upgrade State Machine in the PFL IP Core

After the FPGA powers-up, you have the flexibility to determine whether a factory image or any application image is to be loaded by setting the fpga_pgm[2..0] input pin to the page in which the intended configuration image is stored.

If an error occurs while loading the configuration image, the PFL IP core triggers a reconfiguration to automatically load the factory image. After the FPGA successfully loads the configuration image, the FPGA enters user mode. After the FPGA enters user mode, you can initiate a reconfiguration to a new page by following these steps:

  1. Set the fpga_pgm[2.0] input pin.
  2. Release the pfl_nreset to high if the pfl_nreset is asserted to low.
  3. After fifteen clock cycles, pulse the pfl_nreconfigure input pin to low.
  4. Ensure that all transition is synchronized to pfl_clk.
Figure 16. Transitions Between Different Configurations in Remote System Upgrade
  • The remote system upgrade feature in the PFL IP core does not restrict the factory image to page 0, but allows the factory image to be located on other pages in the flash.
  • You can load the FPGA with either a factory image or any application image after power up, depending on the fpga_pgm[2..0] setting.
Note: The PFL IP core can implement a Last Revision First programming order. The application image is updated with remote system upgrade capabilities. If a flash programming error causes the FPGA configuration to fail, the FPGA is reconfigured from the factory image address. A system shipped from the factory has the same configuration file at the application image address and the factory image address. Intel® recommends that you write-protect the factory image blocks in the flash memory device.